CY7C441-14JC データシートの表示（PDF） - Cypress Semiconductor

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CY7C441-14JC

Clocked 512 x 9, 2K x 9 FIFOs

Cypress Semiconductor 

Switching Waveforms (continued)

Master Reset Timing Diagram[13, 14, 15, 16]

MR

CKW

tSCMR

tPMR

CY7C441

CY7C443

tMRR

ENW

CKR

tSCMR

tMRR

ENR

Q0 – 8

tOHMR

VALID DATA

F1, F2

Read to Empty Timing Diagram[17, 18, 19]

COUNT

3

2

1

0

tAMR

tMRF

ALL DATA

OUTPUTS LOW

C441-8

1

1 (no change)

0

LATENT CYCLE

CKR

ENR

R1

ENABLED

READ

CKW

ENW LOW

F1

R2

ENABLED

READ

R3

ENABLED

READ

R4

FLAG

UPDATE

READ

tSKEW1

tFD

tSKEW2

W1

ENABLED

WRITE

tFD

R5

ENABLED

READ

tFD

F2 LOW

C441-10

Notes:

13. ENW or CKW must be inactive while MR is LOW.

14. ENR or CKR must be inactive while MR is LOW.

15. All data outputs (Q0 – 8) go LOW as a result of the rising edge of MR.

16. In this example, Q0 – 8 will remain valid until tOHMR if the first read shown did not occur or if the read occurred soon enough such that the valid data was

caused by it.

17. “Count” is the number of words in the FIFO.

18. CKR is clock and CKW is opposite clock.

19. R3 updates the flags to the Empty state by bringing F1 LOW. Because W1 occurs greater than tSKEW1 after R3, R3 does not recognize W1 when updating

flag status. But because W1 occurs greater than tSKEW2 before R4, R4 includes W1 in the flag update and therefore updates the FIFO to the Almost Empty

state. It is important to note that R4 is a latent cycle; i.e., it only updates the flag status, regardless of the state of ENR. It does not change the count or the

FIFO’s data outputs.

Document #: 38-06032 Rev. *A

Page 6 of 15

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