CY7C441-14JC データシートの表示（PDF） - Cypress Semiconductor
部品番号
コンポーネント説明
メーカー
CY7C441-14JC Datasheet PDF : 15 Pages
| |||
CY7C441
CY7C443
Switching Waveforms (continued)
Read to Almost Empty Timing Diagram with Read Flag Update Cycle and Free-Running Clocks[17, 18, 21, 22]
COUNT 17 16
17
18 (no change)
18
FLAG UPDATE CYCLE 17
16
15
CKR
ENR
CKW
ENW
R1
R2
ENABLED
READ
tSKEW1
W1
W2
ENABLED
WRITE
R3
R4
FLAG
UPDATE
READ
tSKEW2
W3
W4
ENABLED
WRITE
R5
ENABLED
READ
R6
ENABLED
READ
R7
ENABLED
READ
W5
W6
W7
F1
HIGH
tFD
F2
Write to Almost Full Timing Diagram[17, 23, 24, 25, 26]
COUNT
2030
[494]
2031
[495]
2032
[496]
2031
[495]
CKW
W1
ENABLED
WRITE
W2
ENABLED
WRITE
ENW LOW
CKR
ENR LOW
F1
tSKEW1
R1
ENABLED
READ
tFD
tFD
tFD
C441-12
2030
[494]
2031
[497]
2030
[494]
W3
ENABLED
WRITE
FLAG UPDATE
2032
[498]
2031
[495]
W4
ENABLED
WRITE
2033
[497]
2032
[498]
W5
ENABLED
WRITE
tSKEW2
R2
ENABLED
READ
tFD
tFD
tFD
F2 HIGH
C441-14
Notes:
21. R4 only updates the flag status. It does not affect the count because ENR is HIGH.
22. When making the transition from Almost Empty to Intermediate, the count must increase by two (16 Á18; two enabled writes: W2, W3) before a read (R4)
can update flags to the Intermediate state.
23. CKW is clock and CKR is opposite clock.
24. Count = 2032 indicates Almost Full for CY7C443 and count = 496 indicates Almost Full for CY7C441. Values for the CY7C441 count are shown in brackets.
25. The dashed lines show W3 as flag update write rather than an enabled write because ENW is deasserted.
26. W2 updates the flags to the Almost Full state by bringing F1 LOW. Because R1 occurs greater than tSKEW1 after W2, W2 does not recognize R1 when
updating the flag status. W3 includes R2 in the flag update because R2 occurs greater than tSKEW2 before W3. Note that W3 does not have to be enabled
to update flags.
Document #: 38-06032 Rev. *A
Page 8 of 15
Share Link: 