CY7C441-14JC データシートの表示（PDF） - Cypress Semiconductor
部品番号
コンポーネント説明
メーカー
CY7C441-14JC Datasheet PDF : 15 Pages
| |||
CY7C441
CY7C443
Switching Waveforms (continued)
Write to Almost Full Timing Diagram with Free-Running Clocks[17, 23, 24]
COUNT
CKW
2031
[495]
2032
[496]
W1
ENABLED
WRITE
2031
[495]
W2
2030
[494]
W3
2031
[495]
W4
ENABLED
WRITE
2032
[496]
W5
ENABLED
WRITE
ENW
CKR
ENR
F1
tSKEW1
R1
R2
ENABLED
READ
tFD
tSKEW2
R3
R4
ENABLED
READ
tFD
R5
tFD
2033
[497]
W6
ENABLED
WRITE
R6
F2 HIGH
Write to Almost Full Timing Diagram with Write Flag Update Cycle and Free-Running Clocks[17, 23, 24, 27]
COUNT 2031 2032
[495] [496]
2031
[495]
2030
[494]
2030 (no change)
[494]
FLAG UPDATE CYCLE
2031
[495]
2032
[496]
CKW
W1
W2
ENABLED
WRITE
W3
W4
W5
W6
FLAG
ENABLED
ENABLED
UPDATE
WRITE
WRITE
WRITE
ENW
tSKEW1
tSKEW2
CKR
R1
R2
ENABLED
R3
ENABLED
R4
R5
R6
READ
READ
ENR
tFD
F1
tFD
tFD
C441-13
2033
[497]
W7
ENABLED
WRITE
R7
F2 HIGH
C441-15
Note:
27. When making the transition from Almost Full to Intermediate, the count must decrease by two (2032 Á 2030; two enabled reads: R2, R3) before a write (W4)
can update flags to Intermediate state.
Architecture
Resetting the FIFO
The CY7C441/443 consist of an array of 512/2048 words of 9
bits each (implemented by an array of dual-port RAM cells), a
read pointer, a write pointer, control signals (CKR, CKW, ENR,
ENW, MR), and flags (F1, F2).
Upon power-up, the FIFO must be reset with a Master Reset
(MR) cycle. This causes the FIFO to enter the Empty condition
signified by both flags F1 and F2 being LOW. All data outputs
(Q0–8) go LOW at the rising edge of MR. In order for the FIFO
to reset to its default state, a falling edge must occur on MR
and the user must not read or write while MR is LOW (unless
Document #: 38-06032 Rev. *A
Page 9 of 15
Share Link: 