CY7C68000A データシートの表示（PDF） - Cypress Semiconductor

部品番号

コンポーネント説明

メーカー

CY7C68000A

MoBL-USB™ TX2 USB 2.0 UTMI Transceiver

Cypress Semiconductor 

CY7C68000A

AC Electrical Characteristics

USB 2.0 Transceiver

USB 2.0-compliant in FS and HS modes.

Timing Diagram

HS/FS Interface Timing - 60 MHz

Figure 3. 60 MHz Interface Timing Constraints

CLK

Control_In

DataIn

Control_Out

DataOut

TCSU_MIN

TCH_MIN

TDSU_MIN

TDH_MIN

Table 3. 60 MHz Interface Timing Constraints Parameters

Parameter

TCSU_MIN

TCH_MIN

TDSU_MIN

TDH_MIN

TCCO

TCDO

Description

Minimum setup time for TXValid

Minimum hold time for TXValid

Minimum setup time for Data (transmit direction)

Minimum hold time for Data (transmit direction)

Clock to Control out time for TXReady, RXValid,

RXActive and RXError

Clock to Data out time (Receive direction)

TCCO

TCDO

Min

Typ

Max

Unit

Notes

4

ns

1

ns

4

ns

1

ns

1

8

ns

1

8

ns

Document #: 38-08052 Rev. *H

Page 10 of 15

[+] Feedback

Share Link: