CY7C9335A データシートの表示（PDF） - Cypress Semiconductor
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CY7C9335A Datasheet PDF : 8 Pages
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Pin Configuration
TQFP
Top View
VSS
1
VSS
2
NC
3
NC
4
NC
5
NC
6
NC
7
NC
8
NC
9
OE
10
VSS
11
VCC
12
NC
13
VSS
14
VSS
15
BYPASS
16
NC
17
NC
18
SYNC_EN
19
NC
20
NC
21
DVB_EN
22
NC
23
VCC
24
NC
25
CY7C9335A
75
VSS
74
VCC
73
NC
72
NC
71
NC
70
NC
69
NC
68
NC
67
NC
66
NC
65
CKR
64
VSS
63
NC
62
VCC
61
VSS
60
NC
59
NC
58
SYNC_ERR
57
NC
56
H_SYNC
55
NC
54
NC
53
NC
52
VSS
51
NC
Pin Descriptions CY7C9335A SMPTE-259M Decoder
Name
BYPASS
RF
A/B
H_SYNC
I/O
Input
Output
Output
Output
Description
Bypass SMPTE decoding. BYPASS is ignored if DVB_EN is active (LOW). If BYPASS is HIGH at the
rising edge of CKR (and DVB_EN is HIGH), the data latched into the input register is routed around both
the NRZI decoder and the SMPTE descrambler and presented to the output register. If BYPASS is LOW
at the rising edge of the CKR clock (and DVB_EN is HIGH), the data present in the input register is routed
through the NRZI decoder and SMPTE scrambler.
Reframe. This output is the inverted DVB-EN signal.
CY7B9334 Port Select. When in DVB-ASI mode, this output will alternately select either the INA± or
INB± receiver port based on errors detected in the data stream. This allows CY7C9335A to operate with
normal and inverted DVB-ASI data streams (as would be commonly found on DVB-ASI streams routed
through SMPTE switches). This requires the CY7B9334 INA± and INB± inputs to be connected to the
same signal, but with INB± connected to invert the signal.
Horizontal Sync. This output toggles once every time that the TRS field is recognized. It changes state
one clock cycle prior to the first character of the TRS field (3FF in 10-bit hex) appearing at the PD0−9
outputs. This output also toggles to indicate detection of a TRS sequence, even when the TRS characters
are at a different offset from the present offset and SYNC_EN is active (HIGH). This toggling action is
disabled when DVB_EN is active (LOW).
Document #: 38-02083 Rev. **
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