CY7C9335A データシートの表示（PDF） - Cypress Semiconductor
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CY7C9335A Datasheet PDF : 8 Pages
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CY7C9335A
CY7C9335A Description
Input Register
The input register is clocked by the rising edge of CKR. This
register captures the data present at the D0−9 inputs on every
clock cycle. In addition to the data inputs, all control inputs
except OE are also captured at each rising edge of CKR. This
includes BYPASS, DVB_EN, and SYNC_EN.
NRZI-to-NRZ Decoder
The data in the input register is routed through an
NRZI-to-NRZ decoder prior to being fed to the SMPTE
descrambler. This removes the extra transitions added to the
data stream by the NRZI encoder at the transmit end of the
interface.
SMPTE Descrambler
Once the data has been converted back to NRZ, it is then
routed through a linear feed-forward descrambler. It decodes
the data present in the NRZ decode register using the
X9 + X4 + 1 polynomial to remove the extra transitions added
to the data stream at the transmit end of the interface.
TRS Framer
The TRS Framer is used to detect all 30-bit TRS sequences
(3FF, 000, 000 in 10-bit hex) in the character stream. Anytime
this sequence is detected, the H_SYNC output toggles.
This sequence is also used to frame the received characters
so that the characters delivered to the output register are on
their correct 10-bit boundaries. If SYNC_EN is disabled (LOW)
and the TRS sequence is detected in the decoded data
stream, the character offset register is set to match the offset
of the TRS sequence, and both the TRS sequence and the
following characters are output on their proper 10-bit bound-
aries.
If SYNC_EN is enabled, and a TRS sequence is detected
whose character offset does not match that in the offset
register, an internal flag is set but the offset register is not
updated. On the next consecutive TRS sequence this flag is
cleared and the offset register is updated.
DVB-ASI Operation
The CY7C9335A is designed to operate in both SMPTE-259M
and DVB-ASI environments. When operated in SMPTE-only
environments, the DVB_EN inputs must be tied to VCC or
driven HIGH.
DVB-ASI operation is enabled by asserting DVB_EN LOW.
This signal is latched by the rising edge of the CKR clock.
When the CY7C9335A is placed in DVB mode, the SMPTE
and NRZI decoders are bypassed, and the data latched into
the input register is routed directly to the output register.
Error Detected
Errors detected in the DVB-ASI data stream are indicated by
the Q9 bit being HIGH. The specific type of error is identified
by the remaining Q8−0 bits in the output register.
Command Code Reception
The DVB-ASI interface does not normally transmit any
command characters other than the K28.5 code that is used
both for synchronization and as a fill character when data is
not being transmitted. These K28.5 characters are normally
received as C5.0 characters. If other command characters are
also transmitted, these characters are identified by Q0 being
HIGH, and by the bits present on Q8−1.
DVB Invert Controller
DVB-ASI data streams are use 8B/10B encoded characters. If
these characters are routed through SMPTE switches or
repeaters, the signals may be inverted causing them to
decode into incorrect or illegal characters. The CY7C9335A
contains a state machine that, in conjunction with the
CY7B9334 SMPTE HOTLink receiver, allows inverted
DVB-ASI data streams to be decoded into their correct
characters.
This state machine is only enabled when in DVB mode. It
monitors the data stream for errors, and inverts the data
stream at the CY7B9334 if it exceeds a preset statistical error
rate. For this to operate the A/B output of the CY7C9335A
needs to be connected to the A/B input of the CY7B9334
SMPTE HOTLink receiver (through the appropriate resistive
divider).
If the CY7C9335A is not used for DVB-ASI operation, the A/B
output may be left open.
Document #: 38-02083 Rev. **
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