CYRF69213(2007) データシートの表示（PDF） - Cypress Semiconductor
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CYRF69213 Datasheet PDF : 85 Pages
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CYRF69213
Pinout
Pin
1
2
3, 7, 16
4
5
6, 9, 39
8
10
11
12
13
14, 17, 18, 20,
36
15
19
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
40
41
Name
P0.4
Xtal_in
VCC
P0.3
P0.1
Vbat
P2.1
RF Bias
RFp
GND
RFn
NC
Function
Individually configured GPIO
12 MHz Crystal. External Clock in
Connected to pin 24 via 0.047-µF Capacitor.
Individually configured GPIO
Individually configured GPIO
Connected to pin 24 via 0.047-µFshunt capacitor
GPIO. Port 2 Bit 1
RF pin voltage reference
Differential RF input to/from antenna
Ground
Differential RF to/from antenna
P2.0
RESV
D+
D–
VDD_micro
P1.2 / VREG
P1.3 / nSS
P1.4 / SCK
IRQ
P1.5 / MOSI
MISO
XOUT
PACTL
P1.6
VIO
Reset
P1.7
VDD_1.8
L/D
P0.7
Vreg
E-pad
GPIO. Port 2 Bit 0
Reserved. Must connect to GND
Low-speed USB IO
Low-speed USB IO
4.0–5.5 for 12 MHz CPU/4.75–5.5 for 24 MHz CPU
Must be configured as 3.3V output. It must have a 1–2 µF output capacitor
Slave select SPI Pin
Serial Clock Pin from MCU function to radio function
Interrupt output, configure high/low or GPIO
Master Out Slave In.
Master In Slave Out, from radio function.Can be configured as GPIO
Bufferd CLK, PACTL_n or GPIO
Control for external PA or GPIO
GPIO. Port 1 Bit 6
I/O interface voltage. Connected to pin 24 via 0.047 µF
Radio Reset. Connected to VDD via 0.47 µF Capacitor or to microcontroller GPIO pin. Must
have a RESET = HIGH event the very first time power is applied to the radio otherwise the
state of the radio function control registers is unknown.
GPIO. Port 1 Bit 7
Regulated logic bypass. Connected via 0.47 µF to GND
Connected to GND
GPIO. Port 0 Bit 7
Connected to pin 24
Connected to GND
Document #: 001-07552 Rev. *B
Page 3 of 85
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