MT48LC128M4A2P-7EL データシートの表示（PDF） - Micron Technology

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MT48LC128M4A2P-7EL

Synchronous DRAM

Micron Technology 

512Mb: x4, x8, x16 SDRAM

Functional Description

7. Wait at least tRP time; during this time, NOPs or DESELECT commands must be

given. All banks will complete their precharge, thereby placing the device in the all

banks idle state.

8. Issue an AUTO REFRESH command.

9. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT commands

are allowed.

10. Issue an AUTO REFRESH command.

11. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT commands

are allowed.

12. The SDRAM is now ready for mode register programming. Because the mode register

will power up in an unknown state, it should be loaded with desired bit values prior to

applying any operational command. Using the LMR command, program the mode

register. The mode register is programmed via the MODE REGISTER SET command

with BA1 = 0, BA0 = 0 and retains the stored information until it is programmed again

or the device loses power. Not programming the mode register upon initialization will

result in default settings which may not be desired. Outputs are guaranteed High-Z

after the LMR command is issued. Outputs should be High-Z already before the LMR

command is issued.

13. Wait at least tMRD time, during which only NOP or DESELECT commands are

allowed.

At this point the DRAM is ready for any valid command.

Note:

If desired, more than two AUTO REFRESH commands can be issued in the sequence.

After steps 9 and 10 are complete, repeat them until the desired number of AUTO

REFRESH + tRFC loops is achieved.

PDF: 09005aef809bf8f3/Source: 09005aef80818a4a

512MbSDRAM.fm - Rev. L 10/07 EN

12

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2000 Micron Technology, Inc. All rights reserved.

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