MT48LC128M4A2P-7EL データシートの表示（PDF） - Micron Technology

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MT48LC128M4A2P-7EL

Synchronous DRAM

Micron Technology 

512Mb: x4, x8, x16 SDRAM

Register Definition

Figure 6:

latency is programmed to two clocks, the DQs will start driving after T1 and the data will

be valid by T2, as shown in Figure 6. Table 5 indicates the operating frequencies at which

each CL setting can be used.

Reserved states should not be used as unknown operation or incompatibility with future

versions may result.

CAS Latency

T0

T1

T2

T3

CLK

COMMAND

READ

DQ

NOP

tLZ

tAC

CL = 2

NOP

tOH

DOUT

CLK

COMMAND

T0

READ

DQ

T1

T2

NOP

CL = 3

NOP

tLZ

tAC

T3

T4

NOP

tOH

DOUT

Don’t Care

Undefined

Table 5: CAS Latency

Speed

-7E

-75

Allowable Operating

Frequency (MHz)

CL = 2

≤ 133

≤ 100

CL = 3

≤ 143

≤ 133

Operating Mode

The normal operating mode is selected by setting M7 and M8 to zero; the other combi-

nations of values for M7 and M8 are reserved for future use and/or test modes. The

programmed burst length applies to both READ and WRITE bursts.

Test modes and reserved states should not be used because unknown operation or

incompatibility with future versions may result.

WRITE Burst Mode

When M9 = 0, BL programmed via M0–M2 applies to both READ and WRITE bursts;

when M9 = 1, the programmed burst length applies to READ bursts, but write accesses

are single-location (nonburst) accesses.

PDF: 09005aef809bf8f3/Source: 09005aef80818a4a

512MbSDRAM.fm - Rev. L 10/07 EN

16

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2000 Micron Technology, Inc. All rights reserved.

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