D950CORE データシートの表示（PDF） - STMicroelectronics

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D950CORE

16-Bit Fixed Point Digital Signal Processor (DSP) Core

STMicroelectronics 

D950-Core

When using a pure shift instruction, the TST bit of the CCR is fed by the last bit shifted out.

The shift value provided to the BSU is a signed value which may be provided in three different

ways:

• By the instruction (shift defined in the instruction: see Section 5.4.2).

• By the BSC register (shift defined in the ALU code: if BSC contains a positive

(resp. negative) value, all shifts using BSC content will provide a left (resp.

right) shift).

• By the PSC register (shift defined in the MAC instruction: if PSC contains a

positive (resp. negative) value, all shifts using BSC content will provide a left

(resp. right) shift).

4.1.5 Arithmetic and Logic Unit (ALU)

The D950-Core ALU is 40-bit wide and implements about sixty ALU functions. It includes an

8-bit extension for arithmetical operations.

The calculation mode is controlled by both the instruction and the corresponding bits of the

STA register (see Section 4.5.1). The ALU has two inputs (see Figure 4.2), the left (always

the output of the BSU) and the right (fed by the registers making up the register file).

For logical operations, the ALU is fed with 32-bit wide operands, 0-extended to 40-bits. Then,

the ALU generates a 40-bit result which is always stored in A0 or A1 (A0E and A1E extension

registers being reset).

For arithmetical operations, the ALU is fed with 40-bit wide operands.

• If the operand is an accumulator, the entire 40-bit register (A0E/A0H/A0L or

A1E/A1H/A1L) feeds the 40-bit ALU.

• If not, the 32-bit register is considered as sign extended to a 40-bit format. The

extended ALU then generates a 40-bit wide result which is always stored in

A0E/A0H/A0L or A1E/A1H/A1L

Figure 4.2 D950-Core ALU Operations

FROM BSU

40

FROM

REGISTER

FILE

40

CCR

13

40-bit A.L.U.

8

16

16

8-bit

16-bit

16-bit

A0 or A1

VR02017C

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