D950CORE データシートの表示（PDF） - STMicroelectronics
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D950CORE Datasheet PDF : 89 Pages
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D950-Core
Table 2.2 PROGRAM BUS (35 PINS)
Pin Name
ID0-ID15
IA0-IA15
IRD
IWR
IBS
Type
I/O
O
O
O
O
Description
Instruction data bus.
Hi-Z during cycles with no I-bus exchange.
Instruction address bus.
Hi-Z when in Hold.
I-bus read strobe. Active low.
Hi-Z when in Hold.
I-bus write strobe. Active low.
Hi-Z when in Hold.
I-bus strobe. Active low.
Hi-Z in Hold.
Asserted low at the beginning of a valid I-bus cycle.
Table 2.3 BUS CONTROL (3 PINS)
Pin Name
DTACK
HOLD
HOLDACK
Type
I
I
O
Description
Data transfer acknowledge. Active low.
Sampled on CLKIN rising edge.
Controls bus cycle extension by insertion of wait-states.
Hold bus request signal. Active low.
Asserted by a peripheral (DMA controller) requiring bus mastership. Halts
program execution and tri-states buses.
Hold Acknowledge output. Active low. Indicates that all buses are in Hi-Z.
Table 2.4 GENERAL PURPOSE P-PORT (9 PINS)
Pin Name
P0-P7
P_EN
Type
I/O
O
Description
8-bit bidirectional parallel port. Each pin can be individually programmed as
input or output and as level or falling edge sensitive input conditions for test
by branch and conditional instructions.
Direction of Port
Table 2.5 CLOCK (4 PINS)
Pin Name
CLKIN
CLK_EMU
DMA_CLK
BSU_CLK
Type
I
I
O
O
Clock input.
Emulation Clock input
DMA Clock output
BSU Clock output
Description
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