D950CORE データシートの表示（PDF） - STMicroelectronics

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D950CORE

16-Bit Fixed Point Digital Signal Processor (DSP) Core

STMicroelectronics 

D950-Core

Table 2.6 CONTROL (13 PINS)

Pin Name

IT

ITACK

EOI

LP

LPACK

RESET

MODE

VCI

IRD_WR

INCYCLE

RESET_OUT

STACKX

STACKY

Type

I

O

O

I

O

I

I

O

O

O

O

O

O

Description

Maskable Interrupt Request Input. Falling edge sensitive.

Maskable Interrupt Request Acknowledge. Active Low.

Asserted low at the beginning of Interrupt servicing.

End of maskable Interrupt routine output. Active low.

Asserted low at the end of current interrupt request processing.

Low power. Falling edge sensitive.

Stops the processor after execution of the currently decoded instruction and

enters low-power standby state (in this state, the clock generator is stopped

except for INCYCLE).

Low power Acknowledge. Active low.

Asserted low at the end of execution of the last instruction following detec-

tion of LP falling edge or at the end of LP or STOP instruction.

Reset input. Active low.

Initializes the processor to the RESET state and the clock generator. Forces

Program Counter value to reset address and execution of NOP instruction.

Mode input select.

Forces reset address to 0x0000 (resp. 0xFC00) when low (resp. high).

Valid co-processor instruction decoded.

Asserted high while decoding a co-processor dedicated instruction. Indi-

cates that the co-processor instruction will be executed at the following in-

struction cycle.

Indicates program memory RD/WR cycle during execution of Read or Write

Program memory instruction.

Instruction cycle. Asserted high at the beginning of cycle.

Hardware and Software Reset Output

X Stack read/write instruction

Y Stack read/write instruction

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