DG201 データシートの表示（PDF） - Harris Semiconductor

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DG201

CMOS Dual/Quad SPST Analog Switches

Harris Semiconductor 

Test Circuits

DG200, DG201

ANALOG

INPUT 10V

3V

0V

LOGIC

INPUT

≤2kΩ

10pF

VOUT

1kΩ

NOTE: All channels are turned off by high “1” logic inputs and

all channels are turned on by low “0” inputs; however 0.8V to

2.4V describes the minimum range for switching properly.

Peak input current required for transition is typically -120µA.

FIGURE 5.

3V

0V

LOGIC

INPUT

LOGIC

INPUT *

2VP-P AT 1MHz

ANALOG

INPUT 10V

10,000pF

VOUT

FIGURE 6.

51Ω

VOUT

100Ω

* Pull Down Resistor must be ≤ 2kΩ.

FIGURE 7.

Typical Applications

Using the VREF Terminal

The DG200 and DG201 have an internal voltage divider set-

ting the TTL threshold on the input control lines for V+ equal

to +15V. The schematic shown in Figure 8 with nominal

resistor values, gives approximately 2.4V on the VREF pin.

As the TTL input signal goes from +0.8V to +2.4V, Q1 and

Q2 switch states to turn the switch ON and OFF.

V+ (+15V)

If the power supply voltage is less than +15V, then a resistor

must be added between V+ and the VREF pin, to restore

+2.4V at VREF. The table shows the value of this resistor for

various supply voltages, to maintain TTL compatibility. If

CMOS logic levels on a +5V supply are being used, the

threshold shifts are less critical, but a separate column of

suitable values is given in the table. For logic swings of -5V

to + 5V, no resistor is needed.

In general, the “low” logic level should be <0.8V to prevent

Q1 and Q2 from both being ON together (this will cause

incorrect switch function).

31kΩ

REXT

Q1

VREF

6kΩ

Q2

GATE

PROTECTION

RESISTOR

V+ SUPPLY (V)

+15

+12

+10

+9

+8

+7

TABLE 1.

TTL RESISTOR

(kΩ)

-

100

51

(34)

(27)

18

CMOS RESISTOR

(kΩ)

-

-

-

34

27

18

INPUT

FIGURE 8.

9-18

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