DM9602 データシートの表示（PDF） - Fairchild Semiconductor
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DM9602 Datasheet PDF : 6 Pages
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Operating Rules
1. An external resistor (RX) and external capacitor (CX)
are required as shown in the Logic Diagram.
2. The value of CX may vary from 0 to any necessary
value available. If, however, the capacitor has leakages
approaching 3.0 µA or if stray capacitance from either
terminal to ground is more than 50 pF, the timing equa-
tions may not represent the pulse width obtained.
3. The output pulse with (t) is defined as follows:
where:
RX is in kΩ, CX is in pF
t is in ns
for CX < 103 pF, see Figure 1.
for K vs. CX see Figure 6.
4. If electrolytic type capacitors are to be used, the follow-
ing three configurations are recommended:
1. Use with low leakage capacitors:
The normal RC configuration can be used predict-
ably only if the forward capacitor leakage at 5.0V is
less than 3 µA, and the inverse capacitor leakage
at 1.0V is less than 5 µA over the operational tem-
perature range.
This configuration is not recommended with retriggerable opera-
tion.
5. To obtain variable pulse width by remote trimming, the
following circuit is recommended:
6. Under any operating condition, CX and RX (min) must
be kept as close to the circuit as possible to minimize
stray capacitance and reduce noise pickup.
7. Input Trigger Pulse Rules (See Triggering Truth Table)
Input to Pin 5(11), (Pin 3(13) = HIGH)
Pin 4(12) = LOW
t1, t3 = Min. Positive Input Pulse Width > 40 ns
t2, t4 = Min. Negative Input Pulse Width > 40 ns
R < 0.6 RX (Max)
2. Use with high inverse leakage current electrolytic
capacitors:
The diode in this configuration prevents high
inverse leakage currents through the capacitor by
preventing an inverse voltage across the capacitor.
The use of this configuration is not recommended
with retriggerable operation.
t ≈ 0.3 RCX
3. Use to obtain extended pulse widths:
This configuration can be used to obtain extended
pulse widths, because of the larger timing resistor
allowed by beta multiplication. Electrolytics with
high inverse leakage currents can be used.
R < RX (0.7) (hFE Q1) or < 2.5 MΩ, whichever is the
lesser
RX (min) < RY < RX (max)
(5 kΩ ≤ RY ≤ 10 kΩ is recommended)
Q1: NPN silicon transistor with hFE requirements of
above equations, such as 2N5961 or 2N5962.
t ≈ 0.3 RCX
Input to Pin 4(12) (Pin 3(13) = HIGH)
Pin 5(11) = HIGH
8. The retriggerable pulse width is calculated as shown
below:
The retrigger pulse width is equal to the pulse width (t) plus a delay
time. For pulse widths greater than 500 ns, tW can be approximated as
t. Retriggering will not occur if the retrigger pulse comes within ≈ 0.3
CX (ns) after the initial trigger pulse (i.e., during the discharge cycle).
9. Reset Operation—An overriding clear (active LOW
level) is provided on each one shot. By applying a LOW
to the reset, any timing cycle can be terminated or any
new cycle inhibited until the LOW reset input is
removed. Trigger inputs will not produce spikes in the
output when the reset is held LOW.
10. VCC and Ground wiring should conform to good high
frequency standards so that switching transients on
VCC and Ground leads do not cause interaction
between one shots. Use of a 0.01 to 0.1 µF bypass
capacitor between VCC and Ground located near the
DM9602 is recommended.
Note 1: For further detailed device characteristics and output performance,
please refer to the NSC one-shot application note, AN-366.
www.fairchildsemi.com
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