DS1410E データシートの表示（PDF） - Dallas Semiconductor -> Maxim Integrated

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DS1410E

Parallel Port Adapter

Dallas Semiconductor -> Maxim Integrated 

HOST INTERFACE TIMING DIAGRAMS Figure 3 (cont’d)

DS1410E

tPDH = 2 µs (TYPICAL)

tBLR = 960 µs (MINIMUM) (OD = 0

tBLB = 96 µs (MINIMUM) (OD = 1)

PIN

Input pin

14 ( EN I)

1- WIRE RESET

I/O

DESCRIPTION

Chip enable, driven low to begin 1-Wire I/O.

I

Input pin 11

(O1/ BSY1)

Input pin 13

(O2/ BSY2 )

Input pin 2

(D/ CLK )

Input pin 3

( RES )

Driven low during time slot (to indicate a DS1481 busy condition). Set to state

of I1 after time slot has finished. (O1/ BSY1) will go low after D/ CLK goes low

O if sample of I/O communication was low. Returns to state I1 when ENI goes

back high (see Figure).

Driven low during time slot (to indicate a DS1481 busy condition). Set to state

of 12 after time slot has finished. O2/ BSY2 will go low after D/ CLK goes low

O if sample of I/O communication was low. Returns to state of 12 when ENI

goes back high (see Figure).

Data/Clock pin. Used to specify type of time slot before communication

I

begins. After the time slot has been completed this pin is driven low in order to

solicit the result of the time slot.

Set low (before ENI is driven low) to specify that a reset pulse should be

I generated on the I/O pin.

Output Pin 11

(I1)

I

Can be connected to the O1/ BSY1of another DS1481. May also be connected

to a parallel port printer’s BUSY signal. Internally pulled high via a weak

resistor.

Output Pin 13

Can be connected to the O2/ BSY2 of another DS1481. Can also be connected

(I2)

I to a parallel port printer SELECT OUT signal. Internally pulled high via a

weak resistor

Output Pin 14

( ENO )

O

Set to ENI if not the last part on port. Open drain output with weak internal

pullup resistor.

I/O

I/O 1-Wire I/O line. Bi-directional line with open drain output.

5 of 7

021798

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