DS1609 データシートの表示（PDF） - Dallas Semiconductor -> Maxim Integrated

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DS1609

Dual Port RAM

Dallas Semiconductor -> Maxim Integrated 

DS1609

DUAL PORT RAM TIMING: READ CYCLE

DURING READ CYCLE WE = VIH

AD0 – AD7

CE

OE

ADDRESS VALID

tAS

tAH

DON’T CARE

DATA OUT VALID

tCOE

tOEA

tCEZ

tOEZ

NOTES:

1. During read cycle the address must be off the bus prior to tOEA minimum to avoid bus contention.

2. Read cycles are terminated by the first occurring rising edge of OE or CE.

DUAL PORT RAM TIMING: WRITE CYCLE

DURING WRITE CYCLE OE = VIH

AD0 – AD7

CE

ADDRESS VALID

tAS

tAH

DON’T CARE

DATA IN VALID

tCWE

tDS

tDH

tWP

WE

NOTE:

1. Write cycles are terminated by the first occurring edge of WE or CE.

020499 6/7

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