DS1857 データシートの表示（PDF） - Maxim Integrated

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DS1857

Dual Temperature-Controlled Resistors with External Temperature Input and Monitors

Maxim Integrated 

Dual Temperature-Controlled Resistors with

External Temperature Input and Monitors

PROT

AUX AD

PROT

MAIN MD

PROT

MAIN MD

A0

A1

A2

SDA

SCL

RHIZ

MON1

MON2

VCC

GND

WPEN

AD (AUXILIARY DEVICE ENABLE A0h)

DEVICE

ADDRESS MD (MAIN DEVICE ENABLE)

DEVICE ADDRESS ADDRESS

R/W

ADEN ADFIX

EEPROM

128 x 8 BIT

00h-7Fh

STANDARDS

TABLE

SELECT

ADDRESS

R/W

EEPROM

72 x 8 BIT

80h-C7h

TABLE 02

RESISTOR 0

LOOK-UP

TABLE

TABLE

SELECT

ADDRESS

R/W

EEPROM

72 x 8 BIT

80h-C7h

TABLE 03

RESISTOR 1

LOOK-UP

TABLE

2-WIRE

INTERFACE

ADDRESS

DATA BUS

R/W

ADDRESS

R/W

PROT

MAIN MD

EEPROM

72 x 8 BIT

80h-C7h

MONITORS LIMIT

HIGH

MONITORS LIMIT

LOW

VCC

RRHIZ

SRAM

32 x 8 BIT

60h-7Fh

NOT PROTECTED

TEMP INDEX

MINT (BIT)

TABLE SELECT

TEMP INDEX

TEMP INDEX

RHIZ

H0

RESISTOR 0

50kΩ FULL SCALE

256 POSITIONS

L0

RHIZ

H1

RESISTOR 1

50kΩ FULL SCALE

256 POSITIONS

L1

VCC EXTTMP

MUX

MUX

CTRL

VCC

VCC

RWPEN APEN

MPEN

MEASUREMENT

PROT

MAIN MD R/W

A/D

12-BIT

ALARM FLAGS

TABLE SELECT

ADDRESS

A/D

CTRL

DEVICE ADDRESS

MONITORS LIMIT HIGH

MEASUREMENT

MONITORS LIMIT LOW

PROT AUX

PROT MAIN

COMP CTRL

COMPARATOR

ALARM FLAGS

TABLE 01

EEPROM

16 x 8 BIT

80h-8Fh

VENDOR

INV1 (BIT)

INV2 (BIT)

APEN (BIT)

MPEN (BIT)

ADEN (BIT)

ADFIX (BIT)

MASKING (TMP, VCC, MON1, MON2)

MINT

INTERRUPT

Figure 1. DS1857 Block Diagram

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