DS1863 データシートの表示（PDF） - Maxim Integrated
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DS1863 Datasheet PDF : 62 Pages
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Burst-Mode PON Controller
With Integrated Monitoring
I2C AC ELECTRICAL CHARACTERISTICS
(VCC = +2.85V to +3.9V, TA = -40°C to +95°C, unless otherwise noted, see Figure 9.)
PARAMETER
SCL Clock Frequency
Clock Pulse-Width Low
Clock Pulse-Width High
Bus Free Time Between STOP and
START Condition
SYMBOL
CONDITIONS
fSCL (Note 12)
tLOW
tHIGH
tBUF
START Hold Time
START Setup Time
Data-In Hold Time
Data-In Setup Time
Rise Time of Both SDA and
SCL Signals
tHD:STA
tSU:STA
tHD:DAT
tSU:DAT
tR
(Note 13)
Fall Time of Both SDA and
SCL Signals
tF
(Note 13)
STOP Setup Time
Capacitive Load for Each Bus Line
EEPROM Write Time
tSU:STO
CB
tW
(Note 13)
(Note 14)
MIN TYP
0
1.3
0.6
1.3
0.6
0.6
0
100
20 + 0.1CB
MAX
400
0.9
300
20 + 0.1CB
300
0.6
400
20
UNITS
kHz
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
pF
ms
NONVOLATILE MEMORY CHARACTERISTICS
(VCC = +2.85V to +3.9V, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
EEPROM Write Cycles
+70°C
MIN TYP
50,000
MAX UNITS
Note 1: All voltages are referenced to ground. Currents into the IC are positive and out of the IC are negative.
Note 2: Digital Inputs are at rail. FETG is disconnected SDA = SCL = 1.
Note 3: See the Safety Shutdown (FETG) Output section for details.
Note 4: Eight ranges allow the full-scale range to change from 625mV to 2.5V.
Note 5: This specification applies to the expected full-scale value for the selected range. See the Comp Ranging byte for available
full-scale ranges.
Note 6: Eight ranges allow the full-scale range to change from 312.5mV to 1.25V.
Note 7: The output impedance of the DS1863 is proportional to its scale setting. For instance, if using the 1/2 scale, the output
impedance would be 1.5kΩ.
Note 8: This specification applies to the expected full-scale value for the selected range. See the Mod Ranging byte for available
full-scale ranges.
Note 9: See the APC/Quick-Trip Sample Timing section for details.
Note 10: Assuming an appropriate initial step is programmed that would cause the power to exceed the APC set point within 4
steps, the bias current will be within 1% within the time specified by the binary search time.
Note 11: Guaranteed by design.
Note 12: I2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with I2C stan-
dard-mode timing.
Note 13: CB—total capacitance of one bus line in picofarads.
Note 14: EEPROM write begins after a STOP condition occurs.
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