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DS1921H データシートの表示(PDF) - Maxim Integrated

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DS1921H Datasheet PDF : 45 Pages
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DS1921H/Z
the seven available commands. The protocol for these memory function commands is described in Figure
10. All data is read and written least significant bit first.
DS1921H/Z BLOCK DIAGRAM Figure 1
1-Wire
IO
Port
ROM
Function
Control
64-Bit
Lasered
ROM
Parasite
Powered
Circuitry
Memory
Function
Control
256-Bit
Scratchpad
General-Purpose
SRAM
32.768kHz
Oscillator
Internal
Timekeeping &
Control Reg. &
Counters
Register Page
Alarm Time Stamp
and Duration
Logging Memory
Temperature
Sensor
Control
Logic
Histogram Memory
3V Lithium
Datalog
Memory
PARASITE POWER
The block diagram (Figure 1) shows the parasite-powered circuitry. This circuitry “steals” power when-
ever the IO input is high. IO will provide sufficient power as long as the specified timing and voltage re-
quirements are met. The advantages of parasite power are two-fold: 1) by parasiting off this input, lithium
is conserved, and 2) if the lithium is exhausted for any reason, the ROM may still be read normally.
64-BIT LASERED ROM
Each DS1921 contains a unique ROM code that is 64 bits long. The first eight bits are a 1-Wire family
code. The next 36 bits are a unique serial number. The next 12 bits, called temperature range code, allow
distinguishing the DS1921H and DS1921Z from each other and from other DS1921 versions. The last
eight bits are a CRC of the first 56 bits. See Figure 3 for details. The 1-Wire CRC is generated using a
polynomial generator consisting of a shift register and XOR gates as shown in Figure 4. The polynomial
is X8 + X5 + X4 + 1. Additional information about the Dallas 1-Wire Cyclic Redundancy Check is avail-
able in Application Note 27 and in the Book of DS19xx iButton Standards.
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