DS21Q44 データシートの表示（PDF） - Dallas Semiconductor -> Maxim Integrated
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DS21Q44 Datasheet PDF : 105 Pages
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TABLE OF CONTENTS
DS21Q44
1. INTRODUCTION .............................................................................................................................. 2
2. DS21Q44 PIN DESCRIPTION ......................................................................................................... 7
3. DS21Q44 PIN FUNCTION DESCRIPTION ................................................................................ 13
4. DS21Q44 REGISTER MAP............................................................................................................. 20
5. PARALLEL PORT........................................................................................................................... 24
6. CONTROL, ID AND TEST REGISTERS ..................................................................................... 24
7. STATUS AND INFORMATION REGISTERS............................................................................. 34
8. ERROR COUNT REGISTERS....................................................................................................... 40
9. DS0 MONITORING FUNCTION................................................................................................... 43
10. SIGNALING OPERATION ............................................................................................................ 45
10.1 PROCESSOR BASED SIGNALING........................................................................................ 45
10.2 HARDWARE BASED SIGNALING........................................................................................ 48
11. PER–CHANNEL CODE GENERATION AND LOOPBACK ................................................... 49
11.1 TRANSMIT SIDE CODE GENERATION............................................................................... 49
11.1.1 Simple Idle Code Insertion and Per-Channel Loopback................................................... 49
11.1.2 Per-Channel Code Insertion .............................................................................................. 50
11.2 RECEIVE SIDE CODE GENERATION .................................................................................. 51
12. CLOCK BLOCKING REGISTERS ............................................................................................... 52
13. ELASTIC STORES OPERATION ................................................................................................ 53
13.1 RECEIVE SIDE......................................................................................................................... 54
13.2 TRANSMIT SIDE ..................................................................................................................... 54
14. ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION .................................... 54
14.1 HARDWARE SCHEME ........................................................................................................... 54
14.2 INTERNAL REGISTER SCHEME BASED ON DOUBLE-FRAME ..................................... 55
14.3 INTERNAL REGISTER SCHEME BASED ON CRC4 MULTIFRAME ............................... 57
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