DS21Q43A データシートの表示（PDF） - Dallas Semiconductor -> Maxim Integrated

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DS21Q43A

Quad E1 Framer

Dallas Semiconductor -> Maxim Integrated 

DS21Q43A

Data Bus [D0 to D7] or Address/Data Bus [AD0 to AD7]. In non-multiplexed bus operation (MUX=0),

serves as the data bus. In multiplexed bus operation (MUX=1), serves as an 8-bit multiplexed

address/data bus.

Address Bus [A0 to A5]. In non-multiplexed bus operation (MUX=0), serves as the address bus. In

multiplexed bus operation (MUX=1), these pins are not used and should be tied low.

Bus Type Select [BTS]. Strap high to select Motorola bus timing; strap low to select Intel bus timing.

This pin controls the function of the RD (DS), ALE(AS), and WR (R/ W ) pins. If BTS=1, then these pins

assume the function listed in parentheses ().

Read Input [ RD ] (Data Strobe [DS]).

Framer Selects [FS0 and FS1]. Selects which of the four framers to be accessed.

Chip Selects [ CS ]. Must be low to read or write to any of the four framers.

A6 or Address Latch Enable [ALE] (Address Strobe [AS]). In non-multiplexed bus operation

(MUX=0), serves as the upper address bit. In multiplexed bus operation (MUX=1), serves to demultiplex

the bus on a positive-going edge.

Write Input [ WR ] (Read/Write [R/ W ]).

Positive Supply [VDD]. 5.0 volts ± 0.5 volts.

Signal Ground [VSS]. 0.0 volts.

DS21Q43A FRAMER DECODE Table 1-5

FS1

FS0

0

0

0

1

1

0

1

1

FRAMER ACCESSED

#0

#1

#2

#3

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