DS21Q43A データシートの表示（PDF） - Dallas Semiconductor -> Maxim Integrated

部品番号

コンポーネント説明

メーカー

DS21Q43A

Quad E1 Framer

Dallas Semiconductor -> Maxim Integrated 

DS21Q43A

1.0 INTRODUCTION

The DS21Q43A Quad E1 Framer is made up of five main parts: framer #0, framer #1, framer #2, framer

#3, and the control port which is shared by all four framers. See the Block Diagram in Figure 1-1. Each

of the four framers within the DS21Q43A maintains the same register structure that appeared in the

DS2143. The two framer-select inputs (FS0 and FS1) are used to determine which framer within the

DS21Q43A is being accessed. In this manner, software written for the DS2143 can also be used in the

DS21Q43A with only slight modifications. Several new features have been added to the framers in the

DS21Q43A over the DS2143.

ADDED FEATURE

Non-multiplexed parallel control port operation

Transmit side elastic store

Expanded access to Sa and Si bits

Control signals RFSYNC, RMSYNC, and TFSYNC

FAS word error counting

Code violation counting

Automatic AIS generation upon loss of frame sync

Automatic remote alarm generation

Per-channel signaling insertion

Per-channel loopback from RSER to TSER

Option to update error counters every 62.5 ms

CRC4 resync criteria met status bit

Elastic store reset

Hardware 3-state control

SECTION

2 and 13

10

6

1

5

5

3

3

9 and 11

8 and 11

5

4

10

1

2 of 60

Share Link: