DS2431 データシートの表示（PDF） - Dallas Semiconductor -> Maxim Integrated
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DS2431 Datasheet PDF : 23 Pages
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Figure 2. Hierarchical Structure for 1-Wire Protocol
DS2431: 1024-Bit, 1-Wire EEPROM
DS2431 Command Level:
1-Wire ROM Function
Commands (see Figure 9)
Available
Commands:
Read ROM
Match ROM
Search ROM
Skip ROM
Resume
Overdrive Skip
Overdrive Match
Data Field
Affected:
64-bit Reg. #, RC-Flag
64-bit Reg. #, RC-Flag
64-bit Reg. #, RC-Flag
RC-Flag
RC-Flag
64-bit Reg. #, RC-Flag, OD-Flag
64-bit Reg. #, RC-Flag, OD-Flag
DS2431-specific
Memory Function
Commands (see Figure 7)
Write Scratchpad
Read Scratchpad
Copy Scratchpad
Read Memory
64-bit Scratchpad, Flags
64-bit Scratchpad
Data Memory, Register Page
Data Memory, Register Page
64-BIT LASERED ROM
Each DS2431 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code. The next
48 bits are a unique serial number. The last 8 bits are a CRC (Cyclic Redundancy Check) of the first 56 bits. See
Figure 3 for details. The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and
XOR gates as shown in Figure 4. The polynomial is X8 + X5 + X4 + 1. Additional information about the Dallas 1-Wire
CRC is available in Application Note 27.
The shift register bits are initialized to 0. Then starting with the least significant bit of the family code, one bit at a
time is shifted in. After the 8th bit of the family code has been entered, then the serial number is entered. After the
last bit of the serial number has been entered, the shift register contains the CRC value. Shifting in the 8 bits of the
CRC returns the shift register to all 0s.
Figure 3. 64-Bit Lasered ROM
MSB
8-Bit
CRC Code
MSB
LSB
MSB
Figure 4. 1-Wire CRC Generator
48-Bit Serial Number
Polynomial = X8 + X5 + X4 + 1
LSB
8-Bit Family
Code (2Dh)
LSB MSB
LSB
1st
2nd
3rd
4th
STAGE STAGE STAGE STAGE
X0
X1
X2
X3
5th
STAGE
X4
5 of 23
6th
7th
8th
STAGE STAGE STAGE
X5
X6
X7
X8
INPUT DATA
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