PRELIMINARY
Memory and SHA Functions Flow Chart (continued) Figure 7
DS2432
From Figure 7
3rd Part
33h
N
Compute Next
Secret ?
Y
Bus Master TX
TA1 (T7:T0),
TA2 (T15:T8)
N
Valid Data
Y
Address ?
Bus Master
RX “1”s
Master
N
TX Reset ?
Y
To Figure 7
5th Part
Note: The master must first
load the scratchpad with a
partial secret of 8 bytes
Y
Write-
Protected ?
N
SHA Engine Computes Message *
Authentication Code of Current
Secret, Page Data, and 8 Byte
Partial Secret in Scratchpad
DS2432 Copies a Partial MAC *
to the Secret Register
DS2432 fills Scratchpad with AAh
DS2432 TX “0”
Y
Master
TX Reset ?
N
DS2432 TX “1”
N
Master
TX Reset ?
Y
To Figure 7
3rd Part
*
1-Wire idle high for power
From Figure 7
5th Part
11 of 30