DS2761 データシートの表示（PDF） - Dallas Semiconductor -> Maxim Integrated

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DS2761

High-Precision Li+ Battery Monitor

Dallas Semiconductor -> Maxim Integrated 

Table 1. DETAILED PIN DESCRIPTION

DS2761

SYMBOL DESCRIPTION

CC

Charge Protection Control Output. Controls an external P-channel high-side charge

protection FET.

DC

Discharge Protection Control Output. Controls an external P-channel high-side

discharge protection FET.

DQ

Data Input/Out. 1-Wire data line. Open-drain output driver. Connect this pin to the

DATA terminal of the battery pack. Pin has an internal 1mA pulldown for sensing

disconnection.

PIO

Programmable I/O Pin. Used to control and monitor user-defined external circuitry.

Open drain to VSS.

PLS

Battery Pack Positive Terminal Input. The DS2761 monitors the pack plus terminal

through PLS to detect overcurrent and overload conditions, as well as the presence of a

charge source. Additionally, a charge path to recover a deeply depleted cell is provided

from PLS to VDD. In sleep mode (with SWEN = 0), any capacitance or voltage source

connected to PLS is discharged internally to VSS through 200µA (nominal) to assure

reliable detection of a valid charge source. For details of other internal connections to

PLS and associated conditions see the Li+ Protection Circuitry section.

PS

Power Switch Sense Input. The device wakes up from sleep mode when it senses the

closure of a switch to VSS on this pin. Pin has an internal 1mA pullup to VDD.

VIN

Voltage Sense Input. The voltage of the Li+ cell is monitored through this input pin.

This pin has a weak pullup to VDD.

VDD

Power-Supply Input. Connect to the positive terminal of the Li+ cell through a

decoupling network.

VSS

Device Ground. Connect directly to the negative terminal of the Li+ cell. For the

external sense resistor configuration, connect the sense resistor between VSS and SNS.

SNS

Sense Resistor Connection. Connect to the negative terminal of the battery pack. In the

internal sense resistor configuration, the sense resistor is connected between VSS and

SNS.

IS1

Current-Sense Input. This pin is internally connected to VSS through a 4.7kW resistor.

Connect a 0.1mF capacitor between IS1 and IS2 to complete a lowpass input filter.

IS2

Current-Sense Input. This pin is internally connected to SNS through a 4.7kW resistor.

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