DS28E05R データシートの表示（PDF） - Maxim Integrated

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DS28E05R

1-Wire EEPROM

Maxim Integrated 

DS28E05

1-Wire EEPROM

Electrical Characteristics (continued)

(TA = -40°C to +85°C, unless otherwise noted.) (Note 1)

Note 1: Limits are 100% production tested at TA = +25°C and/or TA = +85°C. Limits over the operating temperature range and rel-

evant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.

Note 2: System requirement.

Note 3: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery

times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times.

Note 4: Typical value represents the internal parasite capacitance when VPUP is first applied. Once the parasite capacitance is

charged, it does not affect normal communication.

Note 5: Guaranteed by design and/or characterization only. Not production tested.

Note 6: VTL, VTH, and VHY are a function of the internal supply voltage, which is a function of VPUP, RPUP, 1-Wire timing, and

capacitive loading on IO. Lower VPUP, higher RPUP, shorter tREC, and heavier capacitive loading all lead to lower values of

VTL, VTH, and VHY.

Note 7: Voltage below which, during a falling edge on IO, a logic 0 is detected.

Note 8: The voltage on IO must be less than or equal to VILMAX at all times the master is driving IO to a logic 0 level.

Note 9: Voltage above which, during a rising edge on IO, a logic 1 is detected.

Note 10: After VTH is crossed during a rising edge on IO, the voltage on IO must drop by at least VHY to be detected as logic 0.

Note 11: The I-V characteristic is linear for voltages less than 1V.

Note 12: Applies to a single device attached to a 1-Wire line.

Note 13: Defines maximum possible bit rate. Equal to 1/(tW0LMIN + tRECMIN).

Note 14: An additional reset or communication sequence cannot begin until the reset high time has expired.

Note 15: Interval after tRSTL during which a bus master can read a logic 0 on IO if there is a DS28E05 present. The power-up pres-

ence detect pulse could be outside this interval but will be complete within 2ms after power-up.

Note 16: ε in Figure 10 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to VTH. The actual

maximum duration for the master to pull the line low is tW1LMAX + tF - ε and tW0LMAX + tF - ε, respectively.

Note 17: δ in Figure 10 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input-high

threshold of the bus master. The actual maximum duration for the master to pull the line low is tRLMAX + tF.

Note 18: Current drawn from IO during the EEPROM programming interval, during which the voltage at IO must not drop below 1.8V.

This condition is met with RPUPMAX over the entire VPUP range.

Note 19: The tPROG interval begins immediately after the trailing rising edge on IO for the last time slot of the Release byte for a

valid Write Memory sequence. Interval ends once the device’s self-timed EEPROM programming cycle is complete and the

current drawn by the device has returned from IPROG to IL.

Note 20: Write-cycle endurance is tested in compliance with JESD47G.

Note 21: Not 100% production tested; guaranteed by reliability monitor sampling.

Note 22: Data retention is tested in compliance with JESD47G.

Note 23: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the

data sheet limit at operating temperature range is established by reliability testing.

Note 24: EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term storage at elevated tem-

peratures is not recommended.

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