DSP56371 データシートの表示（PDF） - Motorola => Freescale
部品番号
コンポーネント説明
メーカー
DSP56371 Datasheet PDF : 102 Pages
| |||
Freescale Semiconductor, Inc.
Serial Host Interface SPI Protocol Timing
Table 7 Serial Host Interface SPI Protocol Timing (continued)
No.
Characteristics1
Mode Expression Min Max Unit
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
Note:
Last SCK edge to SS not asserted
Slave
—
12
—
ns
Data input valid to SCK edge (data
Master/
—
input set-up time)
Slave
0
—
ns
SCK last sampling edge to data input Master/
not valid
Slave
2 ×TC+10
22.4 —
ns
SS assertion to data out active
Slave
—
5
—
ns
SS deassertion to data high
impedance2
Slave
—
—
9
ns
SCK edge to data out valid
(data out delay time)
Master/
Slave
2×TC+10
—
100
ns
SCK edge to data out not valid
(data out hold time)
Master/
Slave
2xTC+10
21.4 —
ns
SS assertion to data out valid
(CPHA = 0)
Slave
TC+9
— 15.0 ns
First SCK sampling edge to HREQ out- Slave
put deassertion
3×TC+30
50
—
ns
Last SCK sampling edge to HREQ out- Slave
put not deasserted (CPHA = 1)
4×TC+30
52.2 —
ns
SS deassertion to HREQ output not
deasserted (CPHA = 0)
Slave
3×TC+30
46.6 —
ns
SS deassertion pulse width (CPHA =
0)
Slave
TC+6
12.7 —
ns
HREQ in assertion to first SCK edge Master 0.5 × tSPICC +
—
—
ns
3×TC+43
HREQ in deassertion to last SCK sam- Master
—
pling edge (HREQ in set-up time)
(CPHA = 1)
0
—
ns
First SCK edge to HREQ in not
Master
—
asserted
(HREQ in hold time)
0
—
ns
HREQ assertion width
Master
3 x TC
ns
1. VCORE_VDD = 1.2 5 ± 0.05 V; TJ = –40°C to 115°C for 150 MHz; TJ = 0°C to 100°C for 181 MHz; CL = 50 pF
2. Periodically sampled, not 100% tested
MOTOROLA
DSP56371 Technical Data
11
For More Information On This Product,
Go to: www.freescale.com
Share Link: 