Freescale Semiconductor, Inc.
AC Electrical Characteristics and Timing
Reset, Stop, Wait, Mode Select, and Interrupt Timing
Reset, Stop, Wait, Mode Select, and Interrupt Timing
(VCC = 5.0 V dc ± 10%, TJ = -40° to +125°C, CL = 50 pF + 1 TTL Load)
cyc = Clock cycle = 1/2 instruction cycle = 2 T cycles
ws = Number of wait states programmed into external bus access using BCR (WS = 0 - 31)
Table 13 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Num
Characteristics
10 RESET Assertion to Address, Data and
Control Signals High Impedance
11 Minimum Stabilization Duration
(See Note 1) OMR bit 6=0
OMR bit 6=1
12 Asynchronous RESET Deassertion to
First External Address Output
(See Note 7)
13 Synchronous Reset Setup Time from
RESET Deassertion to Rising Edge of
CLKO
14 Synchronous Reset Delay Time from
CLKO High to the First External Access
(See Note 7)
15 Mode Select Setup Time
16 Mode Select Hold Time
17 Edge-triggered Interrupt Request Width
18 Delay from IRQA, IRQB Assertion to
External Data Memory Access Out Valid
- Caused by First Interrupt
Instruction Fetch
- Caused by First Interrupt
Instruction Execution
19 Delay from IRQA, IRQB Assertion to
General Purpose Output Valid Caused
by the Execution of the First Interrupt
Instruction
20 Delay from External Data Memory
Address Output Valid Caused by First
Interrupt Instruction Execution to Inter-
rupt Request Deassertion for Level Sen-
sitive Fast Interrupts (See Note 2)
40 MHz
Min
Max
—
25
50 MHz
Min
Max
—
23
600KT
60T
16T
—
600KT
—
60T
18T+20
16T
—
—
18T+17
7
cyc-4
6
cyc-3
16T+3 16T+20 16T+ 3 16T+18
22
—
20
—
0
—
0
—
13
—
11
—
11T+4
—
11T+4
—
19T+4
—
19T+4
—
—
22T+5
22T+4
—
—
5T-26
—
5T-24
+
+
cyc × ws
cyc × ws
60 MHz
Min
Max
—
21
Unit
ns
600KT
—
ns
60T
—
ns
16T
18T+15
ns
5
cyc-2
ns
16T+3 16T+16
ns
18
—
ns
0
—
ns
9
—
ns
11T+3
—
ns
19T+3
—
ns
22T+3
—
ns
—
5T-22
ns
+
cyc × ws
22
DSP56156 Data Sheet
MOTOROLA
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