DSP56156 データシートの表示（PDF） - Motorola => Freescale

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DSP56156

16-bit Digital Signal Processor

Motorola => Freescale 

Freescale Semiconductor, Inc.

AC Electrical Characteristics and Timing

Reset, Stop, Wait, Mode Select, and Interrupt Timing

(VCC = 5.0 V dc ± 10%, TJ = -40° to +125°C, CL = 50 pF + 1 TTL Load)

Table 13 Reset, Stop, Wait, Mode Select, and Interrupt Timing (continued)

Num

Characteristics

40 MHz

Min

Max

50 MHz

Min

Max

60 MHz

Unit

Min

Max

21 Delay from General-Purpose

Output Valid Caused by the

Execution of the First Inter-

rupt Instruction to IRQA,

IRQB Deassertion for Level

Sensitive Fast Interrupts — If

2nd Interrupt Instruction is:

Single Cycle

—

cyc - 29

—

cyc - 27

—

cyc - 26

ns

(See Note 2)

Two Cycles

—

3 cyc - 29

—

3 cyc - 27

—

3 cyc - 26 ns

22 Synchronous setup time from

14

cyc-3

13

cyc-2

12

cyc-1

ns

IRQA, IRQB assertion to

Synchronous falling edge of

CLKO (See Notes 5 and 6)

23 Falling Edge of CLKO to First

Interrupt Vector Address Out

Valid after Synchronous

recovery from Wait State

(See Notes 3 and 5)

27T+3

27T+20

27T+3

27T+18

27T+3

27T+16

ns

24 IRQA Width Assertion to

Recover from Stop State

(See Note 4)

15

—

13

—

12

—

ns

25 Delay from IRQA Assertion to

Fetch of first instruction (exit-

ing Stop)

(See Notes 1 and 3)

OMR bit 6=0 524303T+4

—

524303T+3

—

524303T+3

—

ns

OMR bit 6=1

47T+4

—

47T+3

—

47T+3

—

ns

28 Duration for Level Sensitive

IRQA Assertion to Cause the

Fetch of First IRQA Interrupt

Instruction (exiting Stop)

(See Notes 1 and 3)

OMR bit 6=0 524303T

—

524303T

—

524303T

—

ns

OMR bit 6=1

47T

—

47T

—

47T

—

ns

29 Delay from Level Sensitive

IRQA Assertion to First Inter-

rupt Vector Address Out

Valid (exiting Stop)

(See Notes 1 and 3)

OMR bit 6=0 524303T+4

—

524303T+3

—

524303T+3

—

ns

OMR bit 6=1

47T+4

—

47T+3

—

47T+3

—

ns

MOTOROLA

DSP56156 Data Sheet

23

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