K4S161622D データシートの表示（PDF） - Samsung

部品番号

コンポーネント説明

メーカー

K4S161622D

1M x 16 SDRAM 512K x 16bit x 2 Banks Synchronous DRAM LVTTL

Samsung 

K4S161622D-TI/E

CMOS SDRAM

DC CHARACTERISTICS

(Recommended operating condition unless otherwise noted, Extended TA = -25 to +85°C , Industrial TA = -40 to +85°C)

Parameter

Symbol

Test Condition

CAS

Latency

-50

-55

Version

-60 -70

-80

-10

Unit

Note

Operating Current

(One Bank Active)

Burst Length =1

ICC1

tRC≥tRC(min)

Io = 0 mA

3 125 120 115 105 95 85

mA 2

2

- - - 95 95 80

Precharge Standby Current ICC2P

in power-down mode

ICC2PS

CKE≤VIL(max), tCC = 15ns

CKE & CLK≤VIL(max), tCC = ∞

2

mA

2

ICC2N

Precharge Standby Current

in non power-down mode

ICC2NS

CKE≥VIH(min), CS≥VIH(min), tCC = 15ns

Input signals are changed one time during

30ns

CKE≥VIH(min), CLK≤VIL(max), tCC = ∞

Input signals are stable

15

mA

5

Active Standby Current

in power-down mode

ICC3P CKE≤VIL(max), tCC = 15ns

ICC3PS CKE & CLK≤VIL(max), tCC = ∞

3

mA

3

Active Standby Current

in non power-down mode

(One Bank Active)

ICC3N

CKE≥VIH(min), CS≥VIH(min), tCC = 15ns

Input signals are changed one time during

30ns

ICC3NS

CKE≥VIH(min), CLK≤VIL(max), tCC = ∞

Input signals are stable

25

mA

15

mA

Operating Current

(Burst Mode)

Io = 0 mA

ICC4

Page Burst 2Banks Activated

tCCD = 2CLKs

3 160 155 150 140 130 115

mA 2

2

- - - 115 115 100

Refresh Current

Self Refresh Current

ICC5

ICC6

tRC≥tRC(min)

CKE≤0.2V

3 110 105 100 90 90 80

mA 3

2

- - - 90 90 80

1

mA

Note : 1. Unless otherwise notes, Input level is CMOS(VIH/VIL=VDDQ/VSSQ) in LVTTL.

2. Measured with outputs open. Addresses are changed only one time during tcc(min).

3. Refresh period is 32ms. Addresses are changed only one time during tcc(min).

Rev 1.2 Jan '03

Share Link: