M368L3223DTL データシートの表示（PDF） - Samsung
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M368L3223DTL Datasheet PDF : 12 Pages
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M368L3223DTL
184pin Unbuffered DDR SDRAM MODULE
M368L3223DTL DDR SDRAM 184pin DIMM
32Mx64 DDR SDRAM 184pin DIMM based on 32Mx8
GENERAL DESCRIPTION
The Samsung M368L3223DTL is 32M bit x 64 Double Data
Rate SDRAM high density memory modules. The Samsung
M368L3223DTL consists of eight CMOS 32M x 8 bit with
4banks Double Data Rate SDRAMs in 66pin TSOP-II(400mil)
packages mounted on a 184pin glass-epoxy substrate. Four
0.1uF decoupling capacitors are mounted on the printed circuit
board in parallel for each DDR SDRAM. The M368L3223DTL
is Dual In-line Memory Modules and inten-ded for mounting
into 184pin edge connector sockets.
Synchronous design allows precise cycle control with the use
of system clock. Data I/O transactions are possible on both
edges of DQS. Range of operating frequencies, programmable
latencies and burst lengths allow the same device to be useful
for a variety of high bandwidth, high performance memory sys-
tem applications.
FEATURE
• Performance range
Part No.
Max Freq.
M368L3223DTL-C(L)B3 167MHz(6.0ns@CL=2.5)
M368L3223DTL-C(L)A2 133MHz(7.5ns@CL=2)
M368L3223DTL-C(L)B0 133MHz(7.5ns@CL=2.5)
Interface
SSTL_2
• Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency 2, 2.5 (clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
• Serial presence detect with EEPROM
• PCB : Height 1250 mil, double sided component
PIN CONFIGURATIONS (Front side/back side)
PIN DESCRIPTION
Pin Front Pin Front Pin Front Pin
1 VREF
2 DQ0
3 VSS
4 DQ1
5 DQS0
6 DQ2
7 VDD
8 DQ3
9 NC
10 NC
11 VSS
12 DQ8
13 DQ9
14 DQS1
15 VDDQ
16 CK1
17 /CK1
18 VSS
19 DQ10
20 DQ11
21 CKE0
22 VDDQ
23 DQ16
24 DQ17
25 DQS2
26 VSS
27 A9
28 DQ18
29 A7
30 VDDQ
31 DQ19
32 A 5 62
33 DQ24 63
34 VSS 64
35 DQ25 65
36 DQS3 66
37 A 4 67
38 VDD 68
39 DQ26 69
40 DQ27 70
41 A 2 71
42 VSS 72
43 A 1 73
44 *CB0 74
45 *CB1 75
46 VDD 76
47 *DQS8 77
48 A 0 78
49 *CB2 79
50 VSS 80
51 *CB3 81
52 BA1 82
KEY
83
53 DQ32 84
54 VDDQ 85
55 DQ33 86
56 DQS4 87
57 DQ34 88
58 VSS 89
59 BA0 90
60 DQ35 91
61 DQ40 92
VDDQ 93
/WE 94
DQ41 95
/CAS 96
VSS 9 7
DQS5 98
DQ42 99
DQ43 100
VDD 101
*/CS2 102
DQ48 103
DQ49 104
VSS 105
/CK2 106
CK2 107
VDDQ 108
DQS6 109
DQ50 110
DQ51 111
VSS 112
VDDID 113
DQ56 114
DQ57 115
VDD 116
DQS7 117
DQ58 118
DQ59 119
VSS 120
NC 121
SDA 122
SCL 123
Back
VSS
DQ4
DQ5
VDDQ
DM0
DQ6
DQ7
VSS
NC
NC
NC
VDDQ
DQ12
DQ13
DM1
VDD
DQ14
DQ15
*CKE1
VDDQ
*BA2
DQ20
A12
VSS
DQ21
A11
DM2
VDD
DQ22
A8
DQ23
Pin Back
124 VSS
125
A6
126 DQ28
127 DQ29
128 VDDQ
129 DM3
130
A3
131 DQ30
132 VSS
133 DQ31
134 *CB4
135 *CB5
136 VDDQ
137 CK0
138 /CK0
139 VSS
140 *DM8
141 A10
142 *CB6
143 VDDQ
144 *CB7
KEY
145 VSS
146 DQ36
147 DQ37
148 VDD
149 DM4
150 DQ38
151 DQ39
152 VSS
153 DQ44
Pin Back
154 /RAS
155 DQ45
156 VDDQ
157 /CS0
158 */CS1
159 DM5
160 VSS
161 DQ46
162 DQ47
163 */CS3
164 VDDQ
165 DQ52
166 DQ53
167 *A13
168 VDD
169 DM6
170 DQ54
171 DQ55
172 VDDQ
173 NC
174 DQ60
175 DQ61
176 VSS
177 DM7
178 DQ62
179 DQ63
180 VDDQ
181 SA0
182 SA1
183 SA2
184 VDDSPD
Pin Name
A0 ~ A12
BA0 ~ BA1
Function
Address input (Multiplexed)
Bank Select Address
DQ0 ~ DQ63
DQS0 ~ DQS7
Data input/output
Data Strobe input/output
CK0, CK0 ~ CK2, CK2 Clock input
CKE0
Clock enable input
CS0
RAS
Chip select input
Row address strobe
CAS
Column address strobe
WE
DM0 ~ DM7
VDD
Write enable
Data - in mask
Power supply (2.5V)
VDDQ
VSS
Power Supply for DQS(2.5V)
Ground
VREF
Power supply for reference
VDDSPD
Serial EEPROM Power
Supply (2.3V to 3.6V)
SDA
SCL
SA0 ~ 2
Serial data I/O
Serial clock
Address in EEPROM
VDDID
VDD identification flag
NC
No connection
* These pins are not used in this module.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.2 May. 2002
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