EBE21FD4AHFE-5C-E データシートの表示（PDF） - Elpida Memory, Inc

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EBE21FD4AHFE-5C-E

2GB Fully Buffered DIMM

Elpida Memory, Inc 

EBE21FD4AHFT, EBE21FD4AHFE, EBE21FD4AHFL

Advanced Memory Buffer Block Diagram

Southbound

Data in 10×2

Southbound

10×2 Data out

Reference

clock

1×2

/RESET

PLL

Reset

control

Thermal

sensor

Command

decoder &

CRC check

Core

controller

and CSRs

Demux

RE-time

Re-synch

Data merge

PISO

10×12

failover

Link init SM

and control

and CSRs

10×12

Init

patterns Mux

IBIST-RX

IBIST-TX

LAI logic

4

DRAM clock

4

DRAM clock

DRAM Command

Write data

FIFO

DDR state controller

and CSRs

External MemBIST

DDR calibration

Command

out

Mux

DRAM

29 DRAM

address and

command copy1

interface 29

DRAM

address and

Mux Data out

command copy2

Data in

72+18×2 DRAM

data and strobes

SMBus

Data CRC

generator and

Read FIFO

LAI

controller

Mux

Sync & idle

pattern

generator

NB LAI Buffer

IBIST-TX

IBIST-RX

Link init SM

and control

and CSRs

SMBus

controller

failover

14×6×2

PISO

14×12

Re-synch

Demux

Data merge

RE-time

Northbound 14×2

Data Out

14×2 Northbound

Data In

Note: This figure is a conceptual block diagram of the AMB’s data flow and clock domains.

Preliminary Data Sheet E1001E30 (Ver. 3.0)

4

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