EDE1104AASE データシートの表示（PDF） - Elpida Memory, Inc

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EDE1104AASE

1G bits DDR2 SDRAM

Elpida Memory, Inc 

EDE1104AASE, EDE1108AASE

DC Characteristics 1 (TC = 0°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V)

Parameter

max.

Symbol Grade × 4

×8

Unit

Operating current

(ACT-PRE)

IDD0

-6E TBD TBD

-5C TBD TBD mA

-4A 95

TBD

Operating current

(ACT-READ-PRE)

IDD1

-6E TBD TBD

-5C TBD TBD mA

-4A 105 TBD

Precharge power-

down standby current

IDD2P

-6E

-5C

-4A

TBD

TBD

12

TBD

TBD

TBD

mA

Precharge quiet

standby current

-6E TBD TBD

IDD2Q -5C TBD TBD mA

-4A 35

TBD

-6E TBD TBD

Idle standby current IDD2N -5C TBD TBD mA

-4A 45

TBD

-6E TBD TBD

IDD3P-F -5C TBD TBD mA

Active power-down

-4A 45

TBD

standby current

-6E TBD TBD

IDD3P-S -5C TBD TBD mA

-4A 20

TBD

Active standby

current

-6E TBD TBD

IDD3N -5C TBD TBD mA

-4A 90

TBD

Test condition

one bank; tCK = tCK (IDD), tRC = tRC (IDD),

tRAS = tRAS min.(IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

one bank; IOUT = 0mA;

BL = 4, CL = CL(IDD), AL = 0;

tCK = tCK (IDD), tRC = tRC (IDD),

tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data pattern is same as IDD4W

all banks idle;

tCK = tCK (IDD);

CKE is L;

Other control and address bus inputs are STABLE;

Data bus inputs are FLOATING

all banks idle;

tCK = tCK (IDD);

CKE is H, /CS is H;

Other control and address bus inputs are STABLE;

Data bus inputs are FLOATING

all banks idle;

tCK = tCK (IDD);

CKE is H, /CS is H;

Other control and address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

all banks open;

tCK = tCK (IDD);

CKE is L;

Other control and address

bus inputs are STABLE;

Data bus inputs are

FLOATING

Fast PDN Exit

MRS (12) = 0

Slow PDN Exit

MRS (12) = 1

all banks open;

tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);

CKE is H, /CS is H between valid commands;

Other control and address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

Operating current

-6E TBD TBD

IDD4R -5C TBD TBD mA

(Burst read operating)

-4A 190 TBD

all banks open, continuous burst reads, IOUT = 0mA;

BL = 4, CL = CL(IDD), AL = 0;

tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data pattern is same as IDD4W

Operating current

-6E TBD TBD

(Burst write

IDD4W -5C TBD TBD mA

operating)

-4A 190 TBD

all banks open, continuous burst writes;

BL = 4, CL = CL(IDD), AL = 0;

tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

Data Sheet E0404E20 (Ver. 2.0)

7

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