EDE1108AJBG データシートの表示（PDF） - Elpida Memory, Inc

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EDE1108AJBG

1G bits DDR2 SDRAM

Elpida Memory, Inc 

EDE1108AJBG, EDE1116AJBG

DC Characteristics 1 (TC = 0°C to +85°C, VDD, VDDQ = 1.8V ± 0.1V)

max.

Parameter

Symbol Grade × 8

Operating current

(ACT-PRE)

IDD0

45

Operating current

(ACT-READ-PRE)

IDD1

55

Precharge power-

down standby current

IDD2P

10

Precharge quiet

standby current

IDD2Q

18

Idle standby current IDD2N

20

IDD3P-F

25

Active power-down

standby current

IDD3P-S

13

Active standby current IDD3N

40

Operating current

(Burst read operating)

IDD4R

90

Operating current

(Burst write operating)

IDD4W

95

× 16

Unit Test condition

one bank; tCK = tCK (IDD), tRC = tRC (IDD),

tRAS = tRAS min.(IDD);

55

mA CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

one bank; IOUT = 0mA;

BL = 4, CL = CL(IDD), AL = 0;

tCK = tCK (IDD), tRC = tRC (IDD),

70

mA tRAS = tRAS min.(IDD); tRCD = tRCD (IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data pattern is same as IDD4W

all banks idle;

tCK = tCK (IDD);

10

mA CKE is L;

Other control and address bus inputs are STABLE;

Data bus inputs are FLOATING

all banks idle;

tCK = tCK (IDD);

18

mA CKE is H, /CS is H;

Other control and address bus inputs are STABLE;

Data bus inputs are FLOATING

all banks idle;

tCK = tCK (IDD);

20

mA CKE is H, /CS is H;

Other control and address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

all banks open;

25

mA tCK = tCK (IDD);

CKE is L;

Fast PDN Exit

MRS (12) = 0

Other control and

address bus inputs are

13

mA STABLE;

Data bus inputs are

Slow PDN Exit

MRS (12) = 1

FLOATING

all banks open;

tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP

40

mA

(IDD);

CKE is H, /CS is H between valid commands;

Other control and address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

all banks open, continuous burst reads, IOUT = 0mA;

BL = 4, CL = CL(IDD), AL = 0;

tCK = tCK (IDD), tRAS = tRAS max.(IDD),

115

mA tRP = tRP (IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data pattern is same as IDD4W

all banks open, continuous burst writes;

BL = 4, CL = CL(IDD), AL = 0;

tCK = tCK (IDD), tRAS = tRAS max.(IDD),

125

mA tRP = tRP (IDD);

CKE is H, /CS is H between valid commands;

Address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

Data Sheet E1732E21 (Ver.2.1)

8

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