EDGE629 データシートの表示（PDF） - Semtech Corporation

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EDGE629

1 GHz Timing Deskew and Quad Fanout Element

Semtech Corporation 

Edge629

TEST AND MEASUREMENT PRODUCTS

Circuit Description (continued)

Fine Delay

Fine Delay Select

Fine delay is accomplished using an analog delay cell and

an on-chip 6 bit DAC (see Figure 2). The fine delay range

is designed to be ~2X the coarse delay resolution.

Fine delay provides a total delay span of:

LSB 1 Fine LSB = 2.5 ps (see note)

2 Fine LSB = 5 ps

4 Fine LSB = 10 ps

8 Fine LSB = 20 ps

16 Fine LSB = 40 ps

MSP 32 Fine LSB = 80 ps

0 ns ≤ Fine Delay Range ≤ 157.5 ps.

The fine delay section may be selected or bypassed by a

multiplexer (see Figure 2). If SFD (Select Fine Delay) is

high, Fine Delay will be used. If SFD is low, Fine Delay will

be bypassed.

DAC Code

XXXXXX

000000

111111

SFD

0

1

1

Delay

Fine Delay Bypassed

Minimum Delay (0.0 ns)

Maximum Delay (157 ps)

Note: Because the transfer function is non-linear, some

LSB steps could be as large as 5 ps.

Each channel has its own unique delay setting and may

be programmed independently from all other channels.

The fine delay of any channel will not affect the coarse

delay of that channel, nor will it affect the overall delay of

any other channel.

Fine Delay DAC Outputs

DAC_FINE_(0–3) are analog voltage outputs from the on-

board DACs which program the fine delay elements of

each channel.

DAC_FINE_(0-3) pins are for test purposes only. Nothing

should be connected to these pins.

The propagation delay of a rising and falling edge will track

each other over the entire span of fine delay. (Adding or

subtracting fine delay will not cause pulse width distor-

tion.)

6 Bit DAC

∆T

SFD

Figure 2. Fine Delay Architecture

 2005 Semtech Corp. Rev. 3, 8/1/05

5

www.semtech.com

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