EDS1232CASE データシートの表示（PDF） - Elpida Memory, Inc

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EDS1232CASE

128M bits SDRAM

Elpida Memory, Inc 

EDS1232CASE

Pin Capacitance (TA = 25°C, f = 1MHz)

Parameter

Symbol Pins

min.

typ.

Input capacitance

CI1

Address

1.5

—

CI2

CLK, CKE, /CS, /RAS,

/CAS, /WE, DQM

1.5

—

Data input/output capacitance CI/O

DQ

3.0

—

max.

3.0

3.0

5.5

Unit

Note

pF

pF

pF

AC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 2.5V±0.2V, VSS, VSSQ = 0V)

-1A

Parameter

Symbol

System clock cycle time

(CL = 2)

tCK

(CL = 3)

tCK

CLK high pulse width

tCH

CLK low pulse width

tCL

Access time from CLK

tAC

Data-out hold time

tOH

CLK to Data-out low impedance

tLZ

CLK to Data-out high impedance

tHZ

Input setup time

tSI

Input hold time

tHI

CKE setup time (Power down exit)

ACT to REF/ACT command period

(operation)

(refresh)

tCKSP

tRC

tRC

Active to Precharge command period

tRAS

Active command to column command (same bank) tRCD

Precharge to active command period

tRP

Write recovery or data-in to precharge lead time tDPL

Last data into active latency

tDAL

Active (a) to Active (b) command period

tRRD

Mode register set cycle time

tRSC

Transition time (rise and fall)

Refresh period

(4096 refresh cycles)

tT

tREF

min.

10

10

3

3

—

2

0

2

2

1

2

70

70

50

20

20

20

2CLK + 20ns

20

2

0.5

—

max.

—

—

—

—

6

—

—

6

—

—

—





120000







—

—



30

64

Unit

Note

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

CLK

ns

ms

Data Sheet E0351E30 (Ver. 3.0)

6

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