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5235IS(2005) データシートの表示(PDF) - Intersil

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5235IS
(Rev.:2005)
Intersil
Intersil Intersil
5235IS Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
EL5134, EL5135, EL5234, EL5235
Typical Performance Curves (Continued)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.4
1.2
1 909mW
0.8 870mW
0.6
435mW
0.4
0.2
0
0
SOT23-5/6
θJA=230°C/W
25
50
SO8
θJA=110°C/W
MSOP8/10
θJA=115°C/W
75 85 100 125 150
AMBIENT TEMPERATURE (°C)
FIGURE 35. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1
0.9
0.8
0.7 625mW
0.6
486mW
0.5
0.4
0.3 391mW
0.2
SOT23-5/6
0.1
θJA=265°C/W
SO8
θJA=160°C/W
MSOP8/10
θJA=206°C/W
0
0
25
50
75 85 100 125 150
AMBIENT TEMPERATURE (°C)
FIGURE 36. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
0.15
0.10
0.05
0
-0.05
-0.10
-0.15
0
10 20 30 40 50 60 70 80 90 100
IRE
FIGURE 37. DIFFERENTIAL GAIN (%)
0.15
0.10
0.05
0
-0.05
-0.10
-0.15
-0.20
0
10 20 30 40 50 60 70 80 90 100
IRE
FIGURE 38. DIFFERENTIAL PHASE (°)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
10
FN7383.2
October 3, 2005

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