EL7551 データシートの表示（PDF） - Intersil
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EL7551 Datasheet PDF : 9 Pages
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EL7551
Closed-Loop AC Electrical Specifications
PARAMETER
DESCRIPTION
FOSC
tSYNC
MSS
tBRM
tLEB
DMAX
Oscillator Initial Accuracy
Minimum Oscillator Sync Width
Soft Start Slope
FET Break Before Make Delay
High Side FET Minimum On Time
Maximum Duty Cycle
VS = VIN = 5V, TA = TJ = 25°C, COSC = 1.2nF, unless otherwise specified.
CONDITIONS
MIN
TYP
MAX
105
117
130
25
0.5
15
150
95
UNIT
kHz
ns
V/ms
ns
ns
%
Pin Descriptions
PIN
NUMBER PIN NAME
PIN FUNCTION
1
SGND Control circuit negative supply.
2
COSC Oscillator timing capacitor. FOSC can be approximated by: FOSC (kHz) = 0.1843/COSC, COSC in µF.
3
VDD Control circuit positive supply.
4
PGND Ground return of the regulator. Connected to the source of the low-side synchronous NMOS power FET.
5
PGND Ground return of the regulator. Connected to the source of the low-side synchronous NMOS power FET.
6
VIN
Power supply input of the regulator. Connected to the drain of the high-side NMOS power FET.
7
VIN
Power supply input of the regulator. Connected to the drain of the high-side NMOS power FET.
8
EN
Chip Enable, active high. A 2µA internal pull-up current enables the device if the pin is left open.
9
PGND Ground return of the regulator.
10
VHI
Positive supply of the high-side driver.
11
LX
Inductor drive pin. High current digital output whose average voltage equals the regulator output voltage.
12
LX
Inductor drive pin. High current digital output whose average voltage equals the regulator output voltage.
13
VDRV Positive supply of the low-side driver and input voltage for the high-side boot strap.
14
FB
Voltage feedback input. Connected to an external resistor divider between VOUT and GND. A 125nA pull-up current
forces VOUT to VS in the event that FB is floating.
15
VREF Bandgap reference bypass capacitor. Typically 0.1µF to GND.
16
PGND Ground return of the regulator.
3
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