7457CLZ データシートの表示（PDF） - Intersil

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7457CLZ

40MHz Non-Inverting Quad CMOS Driver

Intersil 

Block Diagram

VS+

INPUT

GND

LEVEL

SHIFTER

EL7457

OE

VH

3-STATE

CONTROL

OUTPUT

VS-

Applications Information

Product Description

The EL7457 is a high performance 40MHz high speed quad

driver. Each channel of the EL7457 consists of a single

P-channel high side driver and a single N-channel low side

driver. These 3Ω devices will pull the output (OUTX) to either

the high or low voltage, on VH and VL respectively,

depending on the input logic signal (INX). It should be noted

that there is only one set of high and low voltage pins.

A common output enable (OE) pin is available on the

EL7457. This pin, when pulled low will put all outputs in to

the high impedance state.

The EL7457 is available in 16-pin SO (0.150"), 16-pin

QSOP, and ultra-small 16-pin QFN packages. The relevant

package should be chosen depending on the calculated

power dissipation.

Supply Voltage Range and Input Compatibility

The EL7457 is designed for operation on supplies from 5V to

15V with 10% tolerance (i.e. 4.5V to 18V). The table on page

6 shows the specifications for the relationship between the

VS+, VS-, VH, VL, and GND pins. The EL7457 does not

contain a true analog switch and therefore VL should always

be less than VH.

All input pins are compatible with both 3V and 5V CMOS

signals With a positive supply (VS+) of 5V, the EL7457 is

also compatible with TTL inputs.

Power Supply Bypassing

When using the EL7457, it is very important to use adequate

power supply bypassing. The high switching currents

developed by the EL7457 necessitate the use of a bypass

capacitor on both the positive and negative supplies. It is

recommended that a 4.7µF tantalum capacitor be used in

parallel with a 0.1µF low-inductance ceramic MLC capacitor.

These should be placed as close to the supply pins as

possible. It is also recommended that the VH and VL pins

have some level of bypassing, especially if the EL7457 is

driving highly capacitive loads.

9

VL

Power Dissipation Calculation

When switching at high speeds, or driving heavy loads, the

EL7457 drive capability is limited by the rise in die

temperature brought about by internal power dissipation. For

reliable operation die temperature must be kept below

TJMAX (125°C). It is necessary to calculate the power

dissipation for a given application prior to selecting package

type.

Power dissipation may be calculated:

4

∑ PD = (VS × IS) + (CINT × VS2 × f) + (CL × VO2 UT × f)

1

(EQ. 1)

where:

VS is the total power supply to the EL7457 (from VS+ to

VS-)

VOUT is the swing on the output (VH - VL)

CL is the load capacitance

CINT is the internal load capacitance (80pF max)

IS is the quiescent supply current (3mA max)

f is frequency

Having obtained the application’s power dissipation, the

maximum junction temperature can be calculated:

TJMAX = TMAX + ΘJA × PD

(EQ. 2)

where:

TJMAX is the maximum junction temperature (125°C)

TMAX is the maximum ambient operating temperature

PD is the power dissipation calculated above

θJA is the thermal resistance, junction to ambient, of the

application (package + PCB combination). Refer to the

Package Power Dissipation curves on page 6.

FN7288.4

January 26, 2012

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