EM78869 データシートの表示（PDF） - ELAN Microelectronics

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EM78869

8-Bit RISC Type Microprocessor

ELAN Microelectronics 

EM78869

8-Bit RISC Type Microprocessor

6.1.9 R8 (Port 8)

Bit 7

R87

Bit 6

R86

Bit 5

R85

Bit 4

R84

Bit 0 ~7: Port 8 8-bit I/O registers

Bit 3

R83

Bit 2

R82

Bit 1

R81

Bit 0

R80

6.1.10 R9 (Port 9)

Bit 7

R97

Bit 6

R96

Bit 5

R95

Bit 4

R94

Bit 0 ~7: Port 9 8-bit I/O registers

Bit 3

R93

Bit 2

R92

Bit 1

R91

Bit 0

R90

6.1.11 RA (Mode Control Register)

Bit 7

IDLE

Bit 6

PLLEN

Bit 5

0

Bit 4

1

Bit 0 ~2: Unused

Bit 3: Reserved. Clear this bit to ‘0.’

Bit 3

0

Bit 2

-

Bit 1

-

Bit 0

-

Bit 4: Reserved. Always set to ‘1.’

Bit 5: Reserved. Clear this bit to '0'.

Bit 6:

(Read/Write) PLL enable signal

0: Disable PLL

1: Enable PLL

The relation between 32.768K and 3.579M (X’TAL) is explained in Fig. 5 below.

OSCI

OSCO

32.8KHz

RC/X'TAL

OSC

PLL

FOSC

0

1

FPLL

Fsystem

"OSCSEL" bit

of Code Option

PLLEN

Bit 7:

Fig 5 The Relation between 32.768KHz and 3.579MHz

(IDLE) Sleep mode selection bit. This bit defines which SLEP instruction is to be

executed.

0: Sleep mode

1: Idle mode

When Sleep mode is defined, program is re-activated by Watch Dog time-out or

Port 9 signal input and resume running from the “Start” vector (0H).

When Idle mode is defined, program is re-activated by TCC clock or Watch Dog

time-out, or by Port 9, 7.0 ~ 7.3 signal input. Program will continue running from the

instruction that follows the “SLEP” instruction.

8 of 34 07.12.2004 (V1.0)

This specification is subject to change without further notice.

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