EM78869 データシートの表示（PDF） - ELAN Microelectronics

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EM78869

8-Bit RISC Type Microprocessor

ELAN Microelectronics 

EM78869

8-Bit RISC Type Microprocessor

Wakeup Signal

SLEEP Mode

RA(7,6)=(0,0)

+ SLEP

TCC Time-Out

X

WDT Time-Out

Port 9

RESET

RESET

Port 7.0 ~ 7.3

X

IDLE Mode

RA(7,6)=(1,0)

+ SLEP

Wake-up

+ Interrupt

+ Next instruction

Wake-up

+ Next instruction

Wake-up

+ Next instruction

Wake-up

+ Interrupt

+ Next instruction

GREEN Mode

RA(7,6)=(x,0)

no SLEP

Interrupt

RESET

X

Interrupt

NORMAL Mode

RA(7,6)=(x,1)

no SLEP

Interrupt

RESET

X

Interrupt

NOTES: P7.0 ~ P7.3 wake-up function is controlled by IOCF (1, 2, 3, 7) and ENI instruction.

P7.0 wakeup signal is a rising or falling signal defined by CONT register Bit 7.

Port 9, Port 7.1, Port 7.2, and Port 7.3 wake-up signals are a falling edge signal.

X=Don’t care

6.1.12 RB (Reserved)

Bit 7

1

Bit 6

1

Bit 5

1

Bit 4

1

Bit 0 ~7: Reserved. Set Bit 7 to Bit 0 to ‘1’.

Bit 3

1

Bit 2

1

Bit 1

1

Bit 0

1

6.1.13 RC (640 Bytes RAM Address)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RAM_A7 RAM_A6 RAM_A5 RAM_A4 RAM_A3 RAM_A2 RAM_A1 RAM_A0

Bit 0 ~7: Select data bank RAM address of up to 256. IOCA is the register for bank

selection.

6.1.14 RD (640 Bytes RAM Data Buffer)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RAM_D7 RAM_D6 RAM_D5 RAM_D4 RAM_D3 RAM_D2 RAM_D1 RAM_D0

Bit 0~7: 640 bytes RAM data transfer register

NOTE

Refer to Section 6.2.8; IOCA Register on how to select RAM bank.

6.1.15 RE (LCD Driver, WDT Control)

Bit 7

0

Bit 6

Bit 5

Bit 4

WDTE WUP9H WUP9L

Bit 3

Bit 2

Bit 1

Bit 0

0

LCD_C2 LCD_C1 LCD_M

Bit 0:

(LCD_M) LCD_M defines the LCD control methods, including duty (see table next

page).

This specification is subject to change without further notice.

07.12.2004 (V1.0) 9 of 34

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