MAX7000B データシートの表示（PDF） - Altera Corporation

部品番号

コンポーネント説明

メーカー

MAX7000B

Programmable Logic Device

Altera Corporation 

MAX 7000B Programmable Logic Device Data Sheet

Figure 1. MAX 7000B Device Block Diagram

INPUT/GCLK1

INPUT/OE2/GCLK2

INPUT/OE1

INPUT/GCLRn

6 or 10 Output Enables (1)

2 to 16 I/O

2 to 16 LAB A

I/O 2 to 16

Control

Block

Macrocells

1 to 16

36

16

6 or 10 Output Enables (1)

LAB B 2 to 16

36

Macrocells

17 to 32

16

2 to 16 I/O

Control

Block

2 to 16 I/O

2 to 16 I/O

6 or 10

2 to 16 LAB C

2 to 16

PIA

2 to 16

LAB D 2 to 16

6 or 10

I/O 2 to 16

Control

Block

Macrocells

33 to 48

36

16

36

Macrocells

49 to 64

16

2 to 16 I/O

Control

Block

2 to 16 I/O

6 or 10

2 to 16

2 to 16

6 or 10

Note:

(1) EPM7032B, EPM7064B, EPM7128B, and EPM7256B devices have six output enables. EPM7512B devices have ten

output enables.

Logic Array Blocks

The MAX 7000B device architecture is based on the linking of

high-performance LABs. LABs consist of 16 macrocell arrays, as shown in

Figure 1. Multiple LABs are linked together via the PIA, a global bus that

is fed by all dedicated input pins, I/O pins, and macrocells.

Each LAB is fed by the following signals:

■ 36 signals from the PIA that are used for general logic inputs

■ Global controls that are used for secondary register functions

■ Direct input paths from I/O pins to the registers that are used for fast

setup times

6

Altera Corporation

Share Link: