FAN480X データシートの表示（PDF） - Fairchild Semiconductor
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FAN480X Datasheet PDF : 17 Pages
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AN-8027
It is typical to set the maximum power limit of PFC stage
around 1.2~1.5 of its nominal power such that the VEA is
around 4~4.5V at nominal output power. By adjusting the
current-sensing resistor for PFC stage, the maximum power
limit of PFC stage can be programmed.
To filter out the current ripple of switching frequency, an
RC filter is typically used for ISENSE pin. RLF1 should not
be larger than 100Ω and the cut-off frequency of filter
should be 1/2~1/6 of the switching frequency.
Diodes D1 and D2 are required to prevent over-voltage on
ISENSE pin due to the inrush current that might damage
the IC. A fast recovery diode or ultra fast recovery diode is
recommended.
where VRAMP is the peak to peak voltage of ramp signal for
current control PWM comparator, which is 2.55V.
The transfer function of the compensation circuit is given as:
vv))CIESA1
=
2π fII
s
1+ s
⋅ 2π fIC
1+ s
(31)
2π fIP
where:
f II
=
GMI
2π ⋅ CIC1
,
f IZ
=
1
2π ⋅ RIC ⋅ CIC1
and
f IP
=
2π
1
⋅ RIC
⋅ CIC 2
(32)
The procedure to design the feedback loop is as follows:
(a) Determine the crossover frequency (fIC) around
1/10~1/6 of the switching frequency. Then calculate
the gain of the transfer function of Equation (30) at
crossover frequency as:
vv))CIESA1
@ f = fIC
=
RCS1 ⋅VBOUT
VRAMP ⋅ 2π fIC ⋅ LBOOST
(33)
(b) Calculate RIC that makes the closed loop gain unity at
crossover frequency:
RIC
=
GMI
⋅
1
vv))CIESA1
@ f = fIC
(34)
Figure 16. Gain Modulation Block
(Design Example) Setting the maximum power limit
of PFC stage as 450W, the current sensing resistor is
obtained as:
RCS1
=
V2
LINE .BO
⋅ GMAX
⋅ RM
R P MAX
IAC BOUT
= 722 ⋅ 9 ⋅ 5.7 ×103
6 ×106 ⋅ 450
= 0.098Ω
Thus, 0.1Ω resistor is selected.
(c) Since the control-to-output transfer function of power
stage has -20dB/dec slope and -90o phase at the
crossover frequency is 0dB, as shown in Figure 17; it
is necessary to place the zero of the compensation
network (fIZ) around 1/3 of the crossover frequency so
that more than 45° phase margin is obtained. Then the
capacitor CIC1 is determined as:
CIC1
=
RIC
1
⋅ 2π
fC
/3
(35)
[STEP-8] PFC Current Loop Design
The transfer function from duty cycle to the inductor
current of boost power stage is given as:
i))L = VBOUT
d sLBOOST
(29)
The transfer function from the output of the current control
error amplifier to the inductor current-sensing voltage is
obtained as:
vv))CIESA1
= RCS1 ⋅VBOUT
VRAMP ⋅ sLBOOST
(30)
(d) Place compensator high-frequency pole (fCP) at least a
decade higher than fIC to ensure that it does not
interfere with the phase margin of the current loop at
its crossover frequency.
CIC 2
=
2π
⋅
1
f IP
⋅ RIC
(36)
© 2009 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 8/26/09
9
www.fairchildsemi.com
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