FAN5009 データシートの表示（PDF） - Fairchild Semiconductor

部品番号

コンポーネント説明

メーカー

FAN5009

Dual Bootstrapped 12V MOSFET Driver

Fairchild Semiconductor 

PRODUCT SPECIFICATION

FAN5009

Thermal Considerations

Total device dissipation:

PD = PQ + PR + PHDRV + PLDRV

(3)

where PQ represents quiescent power dissipation:

PQ = VCC × [4mA + 0.036 (FSW – 100)]

(4)

where FSW is switching frequency (in kHz).

PR is power dissipated in the bootstrap rectifier:

PR = VF × FSW × QG1

(5)

Where QG1 is total gate charge of the upper FET (Q1) for

it’s applied VGS.

VF for the applied IF(AVG) can be graphically determined

using the datasheet curves, where:

IF(AVG) = FSW × QG1

(6)

PHDRV represents internal power dissipation of the upper

FET driver.

PHDRV = PH(R) + PH(F)

(7)

Where PH(R) and PH(F) are internal dissipations for the

rising and falling edges, respectively:

PH(R) = PQ1 × R-----H---U---P---R--+--H---R-U---EP----+-----R----G--

(8)

PH(F) = PQ1 × R-----H---D---N---R--+--H---R-D---EN----+-----R----G--

(9)

where:

PQ1

=

1

2--

×

QG1

×

VGS(Q1)

×

FSW

(10)

RG is the polysilicon gate resistance, internal to the FET.

RE is the external gate drive resistor implemented in many

designs. Note that the introduction of RE can reduce driver

power dissipation, but excess RE may cause errors in the

“adaptive gate drive” circuitry. For more information please

refer to Fairchild app note AN-6003, “Shoot-through” in

Synchronous Buck Converters.

PLDRV is dissipation of the lower FET driver.

PLDRV = PL(R) + PL(F)

(11)

Where PH(R) and PH(F) are internal dissipations for the

rising and falling edges, respectively:

PL(R) = PQ2 × R-----L--U----P---R-+---L--R-U---EP----+-----R----G--

(12)

PL(F) = PQ2 × R-----H---D---N----R-+---L--RD----NE----+-----R----G--

(13)

where:

PQ2

=

1

2--

×

QG2

×

VGS(Q2)

×

FSW

(14)

Layout Considerations

Use the following general guidelines when designing printed

circuit boards (see Figures 6 and 7):

1. Trace out the high-current paths and use short, wide

(>25 mil) traces to make these connections.

2. Connect the PGND pin of the FAN5009 as close as

possible to the source of the lower MOSFET.

3. The VCC bypass capacitor should be located as close as

possible to VCC and PGND pins.

4. Use vias to other layers when possible to maximize

thermal conduction away from the IC.

As described in eq. 8 and 9 above, the total power consumed

in driving the gate is divided in proportion to the resistances

in series with the MOSFET's internal gate node as shown

below:

BOOT

RHUP

HDRV

Q1

R

R

E

G

G

RHDN

S

SW

CBOOT

1

8

2

7

3

6

4

5

CVCC

Figure 5. Driver dissipation model

Figure 6. External component placement

recommendation for SO8 package (not to scale)

REV. 1.0.5 7/22/04

9

Share Link: