FAN54040UCX データシートの表示（PDF） - Fairchild Semiconductor
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FAN54040UCX
Fairchild Semiconductor
FAN54040UCX Datasheet PDF : 41 Pages
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Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable
above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition,
extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute
maximum ratings are stress ratings only.
Symbol
Parameter
VBUS Voltage on VBUS Pin
Continuous
Pulsed, 100 ms Maximum Non-Repetitive
Voltage on PMID Voltage Pin
VI
Voltage on SW, SYS, VBAT, STAT, DIS Pins
VO
dVBUS
dt
Voltage on Other Pins
Maximum VBUS Slope Above 5.5 V when Boost or Charger Active
ESD
Electrostatic Discharge
Protection Level(4)
IEC 61000-4-2 System ESD
Human Body Model per JESD22-A114
Charged Device Model per JESD22-C101
USB Connector
Air Gap
Pins (VBUS to GND) Contact
TJ
Junction Temperature
TSTG Storage Temperature
TL
Lead Soldering Temperature, 10 Seconds
Note:
3. Lesser of 6.5 V or VI + 0.3 V.
4. Guaranteed if CBUS ≥1µF and CMID ≥ 4.7µF.
Min.
-0.3
-1.0
–0.3
–0.3
–0.3
Max.
28.0
7.0
7.0
6.5(3)
4
2000
500
15
8
–40
+150
–65
+150
+260
Unit
V
V
V
V/s
V
kV
°C
°C
°C
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating
conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend
exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
VBUS
VBAT(MAX)
dVBUS
dt
TA
TJ
Supply Voltage
Maximum Battery Voltage when Boost enabled
Negative VBUS Slew Rate during VBUS Short Circuit,
CMID < 4.7 F, see VBUS Short While Charging
TA < 60°C
TA > 60°C
Ambient Temperature
Junction Temperature (see Thermal Regulation and Protection section)
Min.
4
–30
–30
Max.
6
4.5
4
2
+85
+120
Unit
V
V
V/s
°C
°C
Thermal Properties
Junction-to-ambient thermal resistance is a function of application and board layout. This data is measured with four-layer
2s2p boards in accordance to JEDEC standard JESD51. Special attention must be paid not to exceed junction temperature
TJ(max) at a given ambient temperature TA. For measured data, see Table 18.
Symbol
Parameter
JA Junction-to-Ambient Thermal Resistance (see also Figure 18)
JB Junction-to-PCB Thermal Resistance
Typical
50
20
Unit
°C/W
°C/W
© 2012 Fairchild Semiconductor Corporation
FAN54040 – FAN54047 • Rev. 1.0.2
5
www.fairchildsemi.com
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