M50LPW040K データシートの表示（PDF） - STMicroelectronics
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M50LPW040K Datasheet PDF : 36 Pages
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M50LPW040
Figure 2. Logic Diagram (A/A Mux Interface)
VCC VPP
11
A0-A10
8
DQ0-DQ7
RC
M50LPW040
IC
RB
G
W
RP
VSS
AI05436
Figure 3. TSOP Connections
DESCRIPTION
The M50LPW040 is a 4 Mbit (512Kb x8) non-
volatile memory that can be read, erased and
reprogrammed. These operations can be
performed using a single low voltage (3.0 to 3.6V)
supply. For fast programming and fast erasing in
production lines an optional 12V power supply can
be used to reduce the programming and the
erasing times.
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Blocks can be
protected individually to prevent accidental
Program or Erase commands from modifying the
memory. Program and Erase commands are
written to the Command Interface of the memory.
An on-chip Program/Erase Controller simplifies
the process of programming or erasing the
memory by taking care of all of the special
operations that are required to update the memory
contents. The end of a program or erase operation
can be detected and any error conditions
identified. The command set required to control
the memory is consistent with JEDEC standards.
Two different bus interfaces are supported by the
memory. The primary interface is the Low Pin
Count (or LPC) Standard Interface. This has been
designed to remove the need for the ISA bus in
NC
IC (VIH)
NC
NC
NC
NC
A10
NC
RC
VCC
VPP
RP
NC
NC
A9
A8
A7
A6
A5
A4
NC
IC (VIL)
NC
NC
NC
NC
GPI4
NC
CLK
VCC
VPP
RP
NC
NC
GPI3
GPI2
GPI1
GPI0
WP
TBL
1
40
10
31
M50LPW040
11
30
20
21
VSS
VSS
VCC
VCC
LFRAME W
INIT
G
RFU
RB
RFU
DQ7
RFU
DQ6
RFU
DQ5
RFU
DQ4
VCC
VSS
VSS
LAD3
VCC
VSS
VSS
DQ3
LAD2 DQ2
LAD1 DQ1
LAD0 DQ0
ID0
A0
ID1
A1
ID2
A2
RFU
A3
AI05437
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