MT46V16M8-5 データシートの表示（PDF） - Micron Technology
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MT46V16M8-5 Datasheet PDF : 9 Pages
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128Mb: x8
DDR400 SDRAM Addendum
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Notes: 1-5, 14-17, 33; refer to DDR200/266 data sheet for all notes)
(0°C ≤ TA ≤ 50°C; VDDQ = +2.65V ±0.10V, VDD = +2.65V ±0.10V)
AC CHARACTERISTICS
PARAMETER
Access window of DQs from CK/CK#
CK high-level width
CK low-level width
Clock cycle time
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
Address and control input hold time (fast slew rate)
Address and control input setup time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control input setup time (slow slew rate)
Address and control input pulse width
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access
Data Hold Skew Factor
ACTIVE to AUTOPRECHARGE command
ACTIVE to PRECHARGE command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
DQS write preamble setup time
DQS write postamble
Write recovery time
Internal WRITE to READ command delay
Data valid output window
REFRESH to REFRESH command interval
Average periodic refresh interval
Terminating voltage delay to VDD
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
CL = 3
SYMBOL
tAC
tCH
tCL
tCK
tDH
tDS
tDIPW
tDQSCK
tDQSH
tDQSL
tDQSQ
tDQSS
tDSS
tDSH
tHP
tHZ
tLZ
tIH
F
tISF
tIH
S
tIS
S
tIPW
tMRD
tQH
tQHS
tRAP
tRAS
tRC
tRFC
tRCD
tRP
tRPRE
tRPST
tRRD
tWPRE
tWPRES
tWPST
tWR
tWTR
na
tREFC
tREFI
tVTD
tXSNR
tXSRD
-5 (TSOP)
MIN
MAX
-0.6
+0.6
0.45
0.55
0.45
0.55
5
5
0.45
na
0.45
1.4
-0.50
+0.50
0.4
0.4
0.35
0.75
1.25
0.22
0.22
tCH,tCL
+0.60
-0.60
0.75
0.75
na
na
1.8
10
tHP - tQHS
0.50
20
40
70,000
60
70
20
20
0.9
1.1
0.4
0.6
10
0.25
0
0.4
0.6
15
2
tQH - tDQSQ
140.6
15.6
0
75
200
UNITS
ns
tCK
NOTES
30
ns
45,52
ns
26,31
ns
26,31
ns
31
ns
tCK
tCK
ns
25, 26
tCK
tCK
tCK
ns
34
ns
18,42
ns
18,43
ns
14
ns
14
ns
14
ns
14
ns
ns
ns
25, 26
ns
ns
46
ns
35
ns
ns
50
ns
ns
tCK
42
tCK
ns
tCK
ns
20, 21
tCK
19
ns
tCK
ns
25
µs
23
µs
23
ns
ns
tCK
128Mb: x8DDR400 SDRAM
128Mbx8DDR400.p65 – Rev. A (1/30/02-B)
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
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