PDM31096SA10TA データシートの表示（PDF） - Paradigm Technology
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PDM31096SA10TA Datasheet PDF : 8 Pages
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PRELIMINARY
PDM31096
Read Cycle No. 1(4, 5)
tRC
1
ADDR
tAA
tOH
2
DOUT
PREVIOUS DATA VALID
DATA VALID
3
Read Cycle No. 2(2, 4, 6)
tRC
ADDR
4
tAA
tACE
CE
5
tLZCE
tHZCE
OE
6
tLZOE
tHZOE
DOUT
DATA VALID
tAOE
7
AC Electrical Characteristics
Description
-8*
-10*
–12
–15
–20
READ Cycle
READ cycle time
Address access time
Chip enable access time
Output hold from address change
Chip enable to output in low Z(1,3)
Chip disable to output in high Z(1,2,3)
Output enable access time
Output Enable to output in low Z (1,3)
Output disable to output in high Z(1,3)
* Vcc = 3.3V +5%
Sym Min Max Min Max Min Max Min Max Min Max Units
tRC
8 — 10 — 12 — 15 — 20 — ns
tAA
— 8 — 10 — 12 — 15 — 20 ns
tACE — 8 — 10 — 12 — 15 — 20 ns
tOH
3 — 3 — 3 — 3 — 3 — ns
tLZCE 3 — 3 — 3 — 3 — 3 — ns
tHZCE
—
4
—
5—6—7—7
ns
tAOE — 4 — 5 — 6 — 7 — 8 ns
tLZOE 0 — 0 — 0 — 0 — 0 — ns
tHZOE — 4 — 4 — 5 — 6 — 7 ns
8
9
10
11
12
Rev. 2.4 - 5/27/98
5
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