QL3060-0PQ208M データシートの表示（PDF） - QuickLogic Corporation

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QL3060-0PQ208M

Up to 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density

QuickLogic Corporation 

pASIC 3 FPGA Family Data Sheet Rev. D

• Bypass Instruction. The Bypass Instruction allows data to skip a device boundary scan entirely, so the

data passes through the bypass register. The Bypass instruction allows users to test a device without passing

through other devices. The bypass register is connected between the TDI and TDO pins, allowing serial data

to be transferred through a device without affecting the operation of the device.

Pin Descriptions

Pin

TDI

TRSTB

TMS

TCK

TDO

STM

I/ACLK

I/GCLK

I

I/O

VCC

VCCIO

GND

Table 11: Pin Descriptions

Function

Description

Test data in for JTAG

Active low reset for JTAG

Test mode select for JTAG

Hold HIGH during normal operation. Connect to VCC if not

used for JTAG.

Hold LOW during normal operation. Connect to ground if not

used for JTAG.

Hold HIGH during normal operation. Connect to VCC if not

used for JTAG.

Test clock for JTAG

Test data out for JTAG

Hold HIGH or LOW during normal operation. Connect to VCC

or ground if not used for JTAG.

Output that must be left unconnected if not used for JTAG.

Special test mode

Must be grounded during normal operation.

High-drive input and/or array network

driver

Can be configured as either or both.

High-drive input and/or global

network driver

High-drive input

Input/output pin

Can be configured as either or both.

Use for input signals with high fanout.

Can be configured as an input and/or output.

Power supply pin

Input voltage tolerance pin

Connect to 3.3 V supply.

Connect to 5.0 V supply if 5.0 V input tolerance is required,

otherwise connect to 3.3 V supply.

Ground pin

Connect to ground.

10

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