QL3060-0PQ208M データシートの表示（PDF） - QuickLogic Corporation

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QL3060-0PQ208M

Up to 60,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density

QuickLogic Corporation 

pASIC 3 FPGA Family Data Sheet Rev. D

Architecture Overview

The pASIC 3 family of devices have a range of 4,000 to 60,000 usable PLD gates. pASIC 3 FPGAs are

fabricated on a 0.35 µm four-layer metal process using QuickLogic’s“ patented ViaLink“ technology to provide

a unique combination of high performance, high density, low cost, and extreme ease-of-use.

The pASIC 3 family of devices contain a range of 96 to 1,584 logic cells (see Table 1). With a range of 74 to

316 I/Os, the pASIC 3 family is available in many device/package combinations (see Table 2).

Software support for the complete pASIC 3 family is available through two basic packages. The turnkey

QuickWorks package provides the most complete FPGA software solution from design entry to logic

synthesis, to place and route, to simulation. The QuickToolsTM for Workstations package provides a solution

for designers who use Cadence, ExemplarTM, Mentor, Synopsys, Synplicity, ViewlogicTM, AldecTM, or

other third-party tools for design entry, synthesis, or simulation.

© 2005 QuickLogic Corporation

www.quicklogic.com

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